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    • 1. 发明授权
    • Test apparatus and test method
    • 试验装置及试验方法
    • US07904765B2
    • 2011-03-08
    • US11857449
    • 2007-09-19
    • Masahiko HataShinya Sato
    • Masahiko HataShinya Sato
    • G11C29/38G11C29/50
    • G11C29/56G11C16/04G11C29/006G11C2029/0401G11C2029/5602
    • Provided is a test apparatus including: test signal supply sections supplying a test signal writing test data to the connected memory under test, to a terminal of the memory; terminal correspondence determination sections outputting a terminal unit determination result indicating whether test data from the connected terminal matches an expected value; a determination result selection section selecting, for each memory, terminal unit determination results from the terminal correspondence determination sections; a memory correspondence determination section determining whether writing succeeded to each memory, based on the selection result by the determination result selection section; an identifying section identifying a test signal supply section connected to the memory to which writing succeeded and a test signal supply section connected to the memory to which writing failed; and a mask treatment section instructing each test signal supply section whether to perform re-testing, according to whether writing succeeded.
    • 提供了一种测试装置,包括:测试信号提供部分,将测试信号提供给连接的被测试的存储器,将测试数据写入存储器的终端; 终端对应确定部分,输出指示来自所连接终端的测试数据是否匹配期望值的终端单元确定结果; 确定结果选择部分,从终端对应确定部分为每个存储器选择终端单元确定结果; 存储器对应决定部,基于所述判定结果选择部的选择结果,确定是否对每个存储器进行写入; 识别部分,识别连接到写入成功的存储器的测试信号提供部分和连接到写入失败的存储器的测试信号提供部分; 以及掩模处理部,根据写入是否成功指示每个测试信号提供部分是否执行重新测试。
    • 3. 发明授权
    • Silicon carbide single crystal wafer and manufacturing method for same
    • 碳化硅单晶晶片及其制造方法相同
    • US09234297B2
    • 2016-01-12
    • US14241623
    • 2012-08-29
    • Shinya SatoTatsuo FujimotoHiroshi TsugeMasakazu Katsuno
    • Shinya SatoTatsuo FujimotoHiroshi TsugeMasakazu Katsuno
    • B32B3/02C30B23/02C30B29/36C30B23/00H01L29/16
    • C30B23/02C30B23/00C30B29/36H01L29/1608Y10T428/21
    • Provided are a method for manufacturing a SiC single crystal having high crystal quality and, in particular, extremely low screw dislocation density and a SiC single crystal ingot obtained by the method. In particular, provided is a silicon carbide single crystal substrate that is a substrate cut from a bulk silicon carbide single crystal grown by the Physical Vapior Transport (PVT) method, in which the screw dislocation density is smaller in the peripheral region than in the center region, so that screw dislocations are partially reduced.The method is a method for manufacturing a SiC single crystal by the PVT method using a seed crystal and the ingot is a SiC single crystal ingot obtained by the method. Particularly, the silicon carbide single crystal substrate is a silicon carbide single crystal substrate in which when, by representing the diameter of the substrate as R, a center circle region having a diameter of 0.5×R centered around a center point O of the substrate and a doughnut-shaped peripheral region remaining by excluding the center circle region are defined, the average value of screw dislocation densities observed in the doughnut-shaped peripheral region is 80% or less of the average value of screw dislocation densities observed in the center circle region.
    • 提供一种制造具有高结晶质量,特别是极低螺旋位错密度的SiC单晶的方法和通过该方法获得的SiC单晶锭。 特别地,提供了碳化硅单晶基板,其是从通过物理运输(PVT)方法生长的块状碳化硅单晶切割的基板,其中在周边区域中的螺旋位错密度小于中心 区域,使得螺旋位错部分减少。 该方法是通过使用晶种的PVT方法制造SiC单晶的方法,并且该锭是通过该方法获得的SiC单晶锭。 特别地,碳化硅单晶衬底是碳化硅单晶衬底,其中当通过将衬底的直径表示为R时,以衬底的中心点O为中心的直径为0.5×R的中心圆区域, 定义了通过排除中心圆区域而剩余的环状周边区域,在圆环状周边区域观察到的螺旋位错密度的平均值为在中心圆区域观察到的螺旋位错密度的平均值的80%以下 。
    • 4. 发明授权
    • Liquid crystal optical element and optical pickup apparatus
    • 液晶光学元件和光学拾取装置
    • US08891034B2
    • 2014-11-18
    • US12413414
    • 2009-03-27
    • Yoshiharu TakaneShinya SatoNobuhiro Sato
    • Yoshiharu TakaneShinya SatoNobuhiro Sato
    • G02F1/133G02F1/13G09G3/36G02B5/18G11B7/1369G11B7/1353
    • G11B7/1353G02B5/1828G11B7/1369
    • A liquid crystal optical element having a crystal liquid optical element adapted to positively function as a diffraction element and an optical pickup apparatus including the liquid crystal optical element are disclosed. A transparent electrode having a diffraction pattern is arranged on one of a pair of transparent substrates. A liquid crystal panel has a transparent opposed electrode arranged on the other one of the pair of the transparent substrates. A driving unit generates a phase difference distribution in the liquid crystal layer by generating a potential difference between the transparent electrode and the transparent opposed electrode and causes the liquid crystal panel to function as a diffraction element for diffracting the incoming light beam transmitted therethrough. The diffraction pattern or the transparent opposed electrode is divided into a plurality of regions. The driving unit adjusts the potential difference for each of the regions.
    • 公开了一种液晶光学元件,其具有适用于作为衍射元件的结晶液体光学元件和包括该液晶光学元件的光学拾取装置。 具有衍射图案的透明电极设置在一对透明基板中的一个上。 液晶面板具有布置在一对透明基板中的另一个上的透明相对电极。 驱动单元通过产生透明电极和透明相对电极之间的电位差而在液晶层中产生相位差分布,并使液晶面板用作用于衍射透射入射光束的衍射元件。 衍射图案或透明相对电极被分成多个区域。 驱动单元调整每个区域的电位差。
    • 7. 发明授权
    • Test apparatus, and method of manufacturing semiconductor memory
    • 测试装置和制造半导体存储器的方法
    • US07661043B2
    • 2010-02-09
    • US11477245
    • 2006-06-29
    • Shinya Sato
    • Shinya Sato
    • G11C29/00
    • G11C29/56G01R31/31935G11C29/56004
    • A test apparatus includes a pattern memory for storing a test pattern to be inputted to a memory-under-test, an address generating section for sequentially outputting addresses of the memory-under-test into which the test pattern is to be written, a pointer section for sequentially pointing each address of the pattern memory to cause the pattern memory to output the test pattern in synchronism with the address of the memory-under-test outputted out of the address generating section, a bad block memory for storing an address of a bad block of the memory-under-test in advance and a pointer control section for causing the address generating section to output a next address of the memory-under-test while holding the address of the pattern memory outputted out of the pointer section when the address of the memory-under-test generated by the address generating section coincides with any one of addresses stored in the bad block memory.
    • 测试装置包括用于存储要输入到被测存储器的测试模式的模式存储器,地址产生部分,用于顺序地输出要写入测试模式的待测存储器的地址,指针 用于顺序地指示图案存储器的每个地址,使得图案存储器与从地址生成部分输出的被测存储器的地址同步地输出测试图案;坏块存储器,用于存储 预先存储器未测试的坏块和指针控制部分,用于使得地址生成部分在保持从指针部分输出的模式存储器的地址的同时输出待测存储器的下一个地址时 由地址生成部生成的被测存储器的地址与存储在坏块存储器中的任一地址一致。
    • 8. 发明申请
    • NI-BASED CORROSION RESISTANT ALLOY AND CORROSION RESISTANT MEMBER FOR SUPERCRITICAL AMMONIA REACTOR MADE OF THE ALLOY
    • 耐碱耐腐蚀合金及耐腐蚀材料的合金超临界反应器
    • US20090280024A1
    • 2009-11-12
    • US12064297
    • 2006-08-22
    • Yoshihiko YamamuraShinya SatoShinichi Nishiya
    • Yoshihiko YamamuraShinya SatoShinichi Nishiya
    • C22C19/05
    • B01J3/008B01J19/02B01J2219/0236B01J2219/0277B01J2219/029C22C19/052C22C19/053C22C19/055C22C19/056Y02P20/544
    • The invention intends to provide a material that exhibits excellent corrosion resistance to supercritical ammonia and is suitable for a supercritical ammonia reactor.An Ni-based corrosion resistant alloy includes from 15% or more to 50% or less by mass of Cr and any one or both of Mo and W, wherein a [(content of Mo)+0.5×(content of W)] is from 1.5% or more to 8.5% or less by mass, a value of 1.8×[% content of Cr]/{[% content of Mo]+0.5×[% content of W]} is from 3.0 or more to 70.0 or less and the balance is Ni and an unavoidable impurity. Preferably, content of Fe is less than 3% by mass, and content of C is less than 0.05% by mass. The alloy is used to configure a supercritical ammonia reactor or the material is coated on a surface that contacts with a supercritical ammonia fluid. The alloy exhibits excellent corrosion resistance to supercritical ammonia and a mineralizer added the supercritical ammonia. The safety and reliability of an apparatus can be improved, the producing cost can be reduced, the apparatus lifetime can be extended and the running cost can be reduced.
    • 本发明旨在提供一种对超临界氨具有优异耐腐蚀性并适用于超临界氨反应器的材料。 Ni系耐腐蚀合金含有15质量%以上且50质量%以下的Cr和Mo和W中的任一种或两者,其中[(Mo)+ 0.5×(W含量)]为 从1.5%以上至8.5%以下,Crx / {[Mo含量] + 0.5×[W]的含量为1.8×[%]的值为3.0以上至70.0以上, 较少,平衡是Ni和不可避免的杂质。 Fe的含量优选小于3质量%,C的含量优选为0.05质量%以下。 该合金用于构造超临界氨反应器,或者该材料涂覆在与超临界氨流体接触的表面上。 该合金对超临界氨表现出优异的耐腐蚀性,并且矿化剂加入超临界氨。 可以提高设备的安全性和可靠性,可以降低生产成本,延长设备使用寿命,降低运行成本。
    • 10. 发明授权
    • Testing apparatus and a testing method
    • 测试仪器和测试方法
    • US07216271B2
    • 2007-05-08
    • US11097982
    • 2005-04-01
    • Kouichi TanakaMasaru DoiShinya Sato
    • Kouichi TanakaMasaru DoiShinya Sato
    • G11C29/00
    • G01R31/31928G01R31/31922
    • A testing apparatus for performing a setup testing or a hold testing on a device under test (“DUT”) storing a given data signal according to a given clock signal is provided, wherein the testing apparatus includes a timing generating unit for generating sequentially a plurality of timing signals having different timings during the setup testing or the hold testing on the basis of a fist offset value given before starting the setup testing or the hold testing; a pattern generating unit for generating the clock signal and the data signal; a pattern formatting unit for shifting the phase of the data signal with respect to the clock signal sequentially according to the timing signals sequentially generated and providing the DUT with the clock signal and the phase-shifted data signal sequentially; and a determining module for acquiring a setup time or a hold time of the DUT on the basis of storage data which are the data signals stored by the DUT.
    • 提供了一种用于根据给定的时钟信号在被测设备(“DUT”)上执行设置测试或保持测试的测试设备,其中测试设备包括定时产生单元,用于顺序地产生多个 基于在开始建立测试或保持测试之前给出的第一偏移值,在设置测试或保持测试期间具有不同定时的定时信号; 模式产生单元,用于产生时钟信号和数据信号; 模式格式化单元,用于根据顺序生成的定时信号顺序地移动数据信号相对于时钟信号的相位,并且顺序地向DUT提供时钟信号和相移数据信号; 以及确定模块,用于基于作为由DUT存储的数据信号的存储数据获取DUT的建立时间或保持时间。