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    • 6. 发明授权
    • Heterojunction field effect transistor
    • 异质结场效应晶体管
    • US4748484A
    • 1988-05-31
    • US823639
    • 1986-01-29
    • Hidemi TakakuwaYoji Kato
    • Hidemi TakakuwaYoji Kato
    • H01L29/812H01L21/338H01L29/778H01L29/80H01L29/161H01L29/48
    • H01L29/7783
    • A heterojunction field effect transistor according to the invention, comprises: first, second and third semiconductor layers which are sequentially stacked on each other; a first heterojunction formed between said first and second semiconductor layers; a second heterojunction formed between the second and third semiconductor layers; first and second two-dimensional electron gas layers formed in portions of the second semiconductor layer adjacent respectively to the first and second heterojunctions; and a gate electrode, a source electrode and a drain electrode formed on either of the first and third semidconductor layers, wherein the first two-dimensional electron gas layer extends from a portion corresponding to the gate electrode to the drain electrode and has one end virtually connected to the drain electrode, the second two-dimensional electron gas layer extends from a portion corresponding to the gate electrode to the source electrode and has one end virtually connected to the source electrode, and the number of electrons migrating between the first and second two-dimensional electron gas layers is modulated, in the portion of the second semiconductor layer corresponding to the gate electrode, by a voltage to be applied to the gate electrode, thereby controlling a current flowing between the source electrode and the drain electrode. With this structure, an effective gate length is defined by the thickness of the second semiconductor layer. Therefore, when the thickness of the second semiconductor layer is precisely controlled, a gate length can easily be shortened, and a current density can be increased when compared with a conventional device.
    • 根据本发明的异质结场效应晶体管包括:相互堆叠的第一,第二和第三半导体层; 在所述第一和第二半导体层之间形成的第一异质结; 形成在第二和第三半导体层之间的第二异质结; 形成在与第一和第二异质结相邻的第二半导体层的部分中的第一和第二二维电子气层; 以及形成在所述第一和第三半导体层中的任一个上的栅电极,源电极和漏电极,其中所述第一二维电子气层从对应于所述栅电极的部分延伸到所述漏电极,并且具有一端 连接到漏电极,第二二维电子气层从对应于栅电极的部分延伸到源极,并且具有与源电极实际连接的一端,并且在第一和第二二极之间迁移的电子数 在对应于栅电极的第二半导体层的部分中,通过施加到栅电极的电压来调制三维电子气层,从而控制在源电极和漏电极之间流动的电流。 利用这种结构,有效栅极长度由第二半导体层的厚度限定。 因此,当精确地控制第二半导体层的厚度时,与常规器件相比,可以容易地缩短栅极长度,并且可以增加电流密度。
    • 7. 发明授权
    • Semiconductor apparatus
    • 半导体装置
    • US4695862A
    • 1987-09-22
    • US778537
    • 1985-09-20
    • Yoji KatoSeiichi WatanabeMasaru Wada
    • Yoji KatoSeiichi WatanabeMasaru Wada
    • H01L29/73H01L21/331H01L29/10H01L29/732H01L29/735H01L29/72H01L29/80
    • H01L29/735H01L29/1008
    • A semiconductor apparatus which includes a semiconductor substrate with semi-insulating properties and with a first region of a first conductivity type which will become the emitter region and a second region of the same first conductivity type which will become a collector region with the first and second regions formed in the semi-insulating semiconductor substrate and spaced apart from each other and a third region of a second conductivity type formed in the semi-insulating conductor substrate between the first and second regions and with forward biasing voltage applied between the third and first regions so as to form an imaginary base region in the semi-insulating semiconductor substrate beneath the third region due to implanted majority carriers from the third region so that the semiconductor apparatus operates as a bipolar transistor and wherein at least the first and/or the third regions consist of a plurality of regions.
    • 一种半导体装置,包括具有半绝缘特性的半导体衬底和具有第一导电类型的第一区域,该第一区域将成为发射极区域,并且具有相同第一导电类型的第二区域,该第二区域将成为具有第一和第二 形成在半绝缘半导体衬底中并且在第一和第二区域之间形成在半绝缘导体衬底中的第二导电类型的第三区域,并且施加在第三和第一区域之间的正向偏置电压 以便由于从第三区域注入多数载流子而在第三区域下方的半绝缘半导体衬底中形成虚拟基极区域,使得半导体器件作为双极晶体管工作,并且其中至少第一和/或第三区域 由多个区域组成。
    • 8. 发明授权
    • Method for mass preparation of proteoglycan
    • 大量制备蛋白多糖的方法
    • US09284359B2
    • 2016-03-15
    • US13980415
    • 2012-01-19
    • Yoji Kato
    • Yoji Kato
    • C07K14/46C07K14/47A61K31/737
    • C07K14/461A61K31/737C07K14/4725
    • An object of the present invention is to efficiently extract proteoglycan from aquatic animal tissues. The method of the present invention is a method for extracting proteoglycan from fish cartilage, comprising the step of (A) heating small pieces of frozen fish cartilage in water. This method of the present invention enables easy extraction of proteoglycan from fish cartilage with very high efficiency. In particular, the method of the present invention enables extraction of high-molecular-weight proteoglycan. Further, since in the method of the present invention, extraction is performed using only water, it ensures safety in the extraction and safety of the resulting proteoglycan product, compared with hitherto known extraction methods using organic solvents or acids/alkali. Furthermore, the cumbersome step of removing organic solvents is not necessary in the method of the present invention.
    • 本发明的目的是有效地从水生动物组织中提取蛋白多糖。 本发明的方法是从软骨中提取蛋白多糖的方法,其特征在于,包括(A)在水中加热小块冷冻鱼软骨的步骤。 本发明的这种方法能够以非常高的效率容易地从鱼软骨中提取蛋白多糖。 特别地,本发明的方法能够提取高分子量的蛋白多糖。 此外,由于在本发明的方法中,与使用有机溶剂或酸/碱的迄今为止已知的提取方法相比,仅使用水进行提取,因此确保了提取中的安全性和所得到的蛋白多糖产物的安全性。 此外,在本发明的方法中,除去有机溶剂的麻烦步骤是不必要的。
    • 9. 发明授权
    • Method of forming through holes in printed wiring board substrates
    • 在印刷线路板基板上形成通孔的方法
    • US5352325A
    • 1994-10-04
    • US98637
    • 1993-07-28
    • Yoji Kato
    • Yoji Kato
    • H05K3/00H05K3/06H05K3/42B44C1/22B23F1/00B29C37/00
    • H05K3/002H05K2201/09509H05K2201/09836H05K2203/0285H05K2203/0292H05K2203/0554H05K2203/0789H05K2203/0793H05K2203/0796H05K2203/1184H05K3/427
    • The present invention is a method of forming micro through holes in printed wiring board substrate materials by means of chemical etching.In a typical printed wiring board substrate material consisting of a resinous dielectric base material, (which may or may not incorporate glass fibers), clad on both sides by a conductive layer, after the dielectric material in specific locations where through holes are to be formed is exposed by typical processes in which the conductor layer is selectively removed by etching, said exposed dielectric material is first softened, then removed by chemical etching involving several steps and procedures as well as a variety of chemical solutions, under vibratory agitation, forming through holes in said locations of 100 microns diameter or less.Employing the method of the present invention it is possible to determine the position, size and shape of the through hole required and also by means of plating to connect the conductive layers through the dielectric forming micro plated through holes in printed wiring boards.
    • 本发明是通过化学蚀刻在印刷线路板基板材料中形成微通孔的方法。 在由树脂电介质基材(其可以或可以不包括玻璃纤维)组成的典型的印刷线路板基板材料中,在导电层的两侧上包覆在介电材料在要形成通孔的特定位置之后 通过通过蚀刻选择性地去除导体层的典型工艺暴露,首先软化所述暴露的电介质材料,然后通过涉及几个步骤和程序的化学蚀刻以及各种化学溶液在振动搅拌下除去,形成通孔 在直径为100微米或更小的所述位置。 采用本发明的方法,可以确定所需通孔的位置,尺寸和形状,并且还可以通过电镀来连接通过印刷电路板中的电介质形成微电镀通孔的导电层。
    • 10. 发明授权
    • Bipolar transistor and including gas layers between the emitter and base
and the base and collector
    • 双极晶体管,包括发射极和基极之间的气体层以及基极和集电极
    • US4772932A
    • 1988-09-20
    • US812377
    • 1985-12-23
    • Kou TogashiYoji Kato
    • Kou TogashiYoji Kato
    • H01L29/205H01L21/331H01L29/10H01L29/73H01L29/735H01L29/737H01L29/739H01L29/161H01L29/72
    • H01L29/1008H01L29/735H01L29/739
    • A semiconductor device according to the invention comprises: a first semiconductor layer having a low impurity concentration formed on a semiconductor substrate; a second semiconductor layer of a first conductivity type formed on the first semiconductor layer and forming a heterojunction therewith; an emitter region and a collector region formed in the first and second semiconductor layers; and a semiconductor region of a second conductivity type formed in at least the second semiconductor layer between the emitter region and the collector region, wherein two-dimensional electron gas layers, induced in portions of the first semiconductor layer adjacent to the heterojunction and between the emitter region and the semiconductor region and between the collector region and the semiconductor region, are used as current paths, and a virtual base region is formed in the first semiconductor layer below the semiconductor region by majority carriers injected from the semiconductor region into the first semiconductor layer by forward biasing the emitter region and the semiconductor region, thereby enabling a bipolar transistor operation with two dimensional electron gas layers.
    • 根据本发明的半导体器件包括:在半导体衬底上形成的杂质浓度低的第一半导体层; 形成在第一半导体层上并形成异质结的第一导电类型的第二半导体层; 形成在第一和第二半导体层中的发射极区域和集电极区域; 以及形成在所述发射极区域和所述集电极区域之间的至少所述第二半导体层中的第二导电类型的半导体区域,其中在所述第一半导体层的与所述异质结相邻的部分和所述发射极之间诱发的二维电子气体层 区域和半导体区域之间以及集电极区域和半导体区域之间的半导体区域用作电流路径,并且通过从半导体区域注入第一半导体层的多数载流子在半导体区域下方的第一半导体层中形成虚拟基极区域 通过使发射极区域和半导体区域向前偏置,从而能够利用二维电子气体层进行双极晶体管工作。