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1. 发明申请

US20060097399A1 Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program product 失效
标题翻译：产生图案的方法，制造半导体器件的方法，半导体器件和计算机程序产品
公开(公告)号：US20060097399A1
公开(公告)日：2006-05-11
申请号：US11265231
申请日：2005-11-03
申请人： Masaaki Hatano , Motoya Okazaki , Junichi Wada , Takeshi Nishioka , Hisashi Kaneko , Takeshi Fujimaki , Kazuyuki Higashi , Kenji Yoshida , Noriaki Matsunaga
发明人： Masaaki Hatano , Motoya Okazaki , Junichi Wada , Takeshi Nishioka , Hisashi Kaneko , Takeshi Fujimaki , Kazuyuki Higashi , Kenji Yoshida , Noriaki Matsunaga
IPC分类号： H01L23/48
CPC分类号： G06F17/5068
摘要： A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.
摘要翻译：一种用于产生图案的方法包括：读出互连布局和孔布局;布置规定互连图案的布局布局;布置配置为连接到互连图案的孔图案的孔布局; 在图案处理区域中将在相同互连层级中连接的孔图案中的一个提取到所述互连图案之一; 提取包括所提取的孔图案的第一处理区域; 计算包括在第一处理区域中的互连图案的第一图案密度; 以及基于所述第一图案密度在所述第一处理区域中生成第一附加图案。

2. 发明授权

US07996813B2 Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program 有权
标题翻译：用于生成图案的方法，制造半导体器件的方法，半导体器件和计算机程序
公开(公告)号：US07996813B2
公开(公告)日：2011-08-09
申请号：US12654865
申请日：2010-01-07
申请人： Masaaki Hatano , Motoya Okazaki , Junichi Wada , Takeshi Nishioka , Hisashi Kaneko , Takeshi Fujimaki , Kazuyuki Higashi , Kenji Yoshida , Noriaki Matsunaga
发明人： Masaaki Hatano , Motoya Okazaki , Junichi Wada , Takeshi Nishioka , Hisashi Kaneko , Takeshi Fujimaki , Kazuyuki Higashi , Kenji Yoshida , Noriaki Matsunaga
IPC分类号： G06F15/04
CPC分类号： G06F17/5068
摘要： A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.
摘要翻译：一种用于产生图案的方法包括：读出互连布局和孔布局;布置规定互连图案的布局布局;布置配置为连接到互连图案的孔图案的孔布局; 在图案处理区域中将在相同互连层级中连接的孔图案中的一个提取到所述互连图案之一; 提取包括所提取的孔图案的第一处理区域; 计算包括在第一处理区域中的互连图案的第一图案密度; 以及基于所述第一图案密度在所述第一处理区域中生成第一附加图案。

3. 发明授权

US07667332B2 Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program product 失效
标题翻译：产生图案的方法，制造半导体器件的方法，半导体器件和计算机程序产品
公开(公告)号：US07667332B2
公开(公告)日：2010-02-23
申请号：US11265231
申请日：2005-11-03
申请人： Masaaki Hatano , Motoya Okazaki , Junichi Wada , Takeshi Nishioka , Hisashi Kaneko , Takeshi Fujimaki , Kazuyuki Higashi , Kenji Yoshida , Noriaki Matsunaga
发明人： Masaaki Hatano , Motoya Okazaki , Junichi Wada , Takeshi Nishioka , Hisashi Kaneko , Takeshi Fujimaki , Kazuyuki Higashi , Kenji Yoshida , Noriaki Matsunaga
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： G06F17/5068
摘要： A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.
摘要翻译：一种用于产生图案的方法包括：读出互连布局和孔布局;布置规定互连图案的布局布局;布置配置为连接到互连图案的孔图案的孔布局; 在图案处理区域中将在相同互连层级中连接的孔图案中的一个提取到所述互连图案之一; 提取包括所提取的孔图案的第一处理区域; 计算包括在第一处理区域中的互连图案的第一图案密度; 以及基于所述第一图案密度在所述第一处理区域中生成第一附加图案。

4. 发明申请

US20100115479A1 Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program 有权
标题翻译：用于生成图案的方法，制造半导体器件的方法，半导体器件和计算机程序
公开(公告)号：US20100115479A1
公开(公告)日：2010-05-06
申请号：US12654865
申请日：2010-01-07
申请人： Masaaki Hatano , Motoya Okazaki , Junichi Wada , Takeshi Nishioka , Hisashi Kaneko , Takeshi Fujimaki , Kazuyuki Higashi , Kanji Yoshida , Noriaki Matsunaga
发明人： Masaaki Hatano , Motoya Okazaki , Junichi Wada , Takeshi Nishioka , Hisashi Kaneko , Takeshi Fujimaki , Kazuyuki Higashi , Kanji Yoshida , Noriaki Matsunaga
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.
摘要翻译：一种用于产生图案的方法包括：读出互连布局和孔布局;布置规定互连图案的布局布局;布置配置为连接到互连图案的孔图案的孔布局; 在图案处理区域中将在相同互连层级中连接的孔图案中的一个提取到所述互连图案之一; 提取包括所提取的孔图案的第一处理区域; 计算包括在第一处理区域中的互连图案的第一图案密度; 以及基于所述第一图案密度在所述第一处理区域中生成第一附加图案。

5. 发明授权

US07308395B2 Simulation circuit pattern evaluation method, manufacturing method of semiconductor integrated circuit, test substrate, and test substrate group 有权
标题翻译：模拟电路图案评估方法，半导体集成电路制造方法，测试基板和测试基板组
公开(公告)号：US07308395B2
公开(公告)日：2007-12-11
申请号：US10757415
申请日：2004-01-15
申请人： Hisashi Kaneko , Motoya Okazaki , Hiroyuki Toshima
发明人： Hisashi Kaneko , Motoya Okazaki , Hiroyuki Toshima
IPC分类号： G06F17/50 , G06F9/455 , H01L21/66 , G01R31/26
CPC分类号： G06F17/5068
摘要： According to an aspect of the present invention, there is provided a simulation circuit pattern evaluation method including: designing an aggregate of simulation circuit patterns, which simulate a circuit pattern of a semiconductor integrated circuit, by combining plural geometrical structure defining parameters respectively having at least two states in such a manner that the respective states appear the same number of times in the respective geometrical structure defining parameters; forming the aggregate of the simulation circuit patterns on a substrate; and evaluating the formed aggregate of the simulation circuit patterns.
摘要翻译：根据本发明的一个方面，提供了一种仿真电路图案评估方法，包括：通过组合多个几何结构来设计模拟电路图案的集合，模拟电路图案模拟半导体集成电路的电路图案，两种状态使得各个状态在相应的几何结构定义参数中出现相同的次数; 在基板上形成模拟电路图案的集合体; 并对所形成的仿真电路图案进行评估。

6. 发明申请

US20050075854A1 Simulation circuit pattern evaluation method, manufacturing method of semiconductor integrated circuit, test substrate, and test substrate group 有权
标题翻译：模拟电路图案评估方法，半导体集成电路制造方法，测试基板和测试基板组
公开(公告)号：US20050075854A1
公开(公告)日：2005-04-07
申请号：US10757415
申请日：2004-01-15
申请人： Hisashi Kaneko , Motoya Okazaki , Hiroyuki Toshima
发明人： Hisashi Kaneko , Motoya Okazaki , Hiroyuki Toshima
IPC分类号： H01L21/66 , G06F17/50 , H01L21/3205 , H01L21/768 , H01L23/52 , G06F9/45
CPC分类号： G06F17/5068
摘要： According to an aspect of the present invention, there is provided a simulation circuit pattern evaluation method including: designing an aggregate of simulation circuit patterns, which simulate a circuit pattern of a semiconductor integrated circuit, by combining plural geometrical structure defining parameters respectively having at least two states in such a manner that the respective states appear the same number of times in the respective geometrical structure defining parameters; forming the aggregate of the simulation circuit patterns on a substrate; and evaluating the formed aggregate of the simulation circuit patterns.
摘要翻译：根据本发明的一个方面，提供了一种仿真电路图案评估方法，包括：通过组合多个几何结构来设计模拟电路图案的集合，模拟电路图案模拟半导体集成电路的电路图案，两种状态使得各个状态在相应的几何结构定义参数中出现相同的次数; 在基板上形成模拟电路图案的集合体; 并对所形成的仿真电路图案进行评估。

7. 发明授权

US08758596B2 Hydrogenation isomerization catalyst, method for producing same, method for dewaxing hydrocarbon oil, and method for producing lubricant base oil 有权
标题翻译：氢化异构化催化剂，其制造方法，烃油的脱蜡方法，以及润滑油基础油的制造方法
公开(公告)号：US08758596B2
公开(公告)日：2014-06-24
申请号：US13140144
申请日：2009-12-25
申请人： Kazuaki Hayasaka , Motoya Okazaki , Mayumi Yokoi
发明人： Kazuaki Hayasaka , Motoya Okazaki , Mayumi Yokoi
IPC分类号： C10G73/02
CPC分类号： C10M177/00 , B01J29/7261 , B01J29/7284 , B01J29/7292 , B01J29/7461 , B01J29/7484 , B01J29/7492 , B01J29/7861 , B01J29/7884 , B01J29/7892 , B01J35/002 , B01J37/0009 , B01J37/0201 , B01J2229/42 , C10G45/64 , C10G2300/1022 , C10G2300/1074 , C10G2300/1077 , C10G2400/10 , C10N2270/00
摘要： A first hydroisomerization catalyst contains a support being a extruded product prepared by calcination having a thermal treatment that includes thermally treating at 350° C. or more and at least one metal supported on the support and selected from the group consisting of metals belonging to Groups 8 to 10 of the periodic table, molybdenum and tungsten, wherein the support contains (a1) a calcined zeolite prepared by calcination having a thermal treatment that includes thermally treating at 350° C. or more of an ion-exchanged zeolite obtained by ion exchange of an organic template-containing zeolite containing an organic template and having a 10-membered ring one-dimensional porous structure in a solution containing ammonium ions and/or protons, and (b1) a calcined inorganic oxide prepared by calcination having a thermal treatment that includes thermally treating at 350° C. or more of one inorganic oxide selected from the group consisting of alumina, silica, titania, boria, zirconia, magnesia, ceria, zinc oxide, phosphorus oxide, and a composite oxide containing a combination of two or more of these oxides, wherein the thermal treatment to which the calcined zeolite has been subjected includes calcination in which the ion-exchanged zeolite that has not been thermally treated at 350° C. or more is heated within the range of 350° C. to 450° C.
摘要翻译：第一加氢异构化催化剂含有载体，其为通过煅烧制备的挤出产物，该热处理包括在350℃或更高温度下热处理和至少一种负载在载体上的金属，并且选自属于第8族的金属至（10）的元素周期表中的钼和钨，其中所述载体包含（a1）通过煅烧制备的煅烧沸石，其具有热处理，所述热处理包括在350℃或更高温度下热处理通过离子交换获得的离子交换沸石含有有机模板的沸石，含有有机模板，并且在含有铵离子和/或质子的溶液中具有10元环一维多孔结构，（b1）通过煅烧制备的煅烧无机氧化物，其具有热处理，所述热处理包括在350℃以上的一种无机氧化物热处理，其选自氧化铝，二氧化硅，二氧化钛，氧化硼，氧化锆，氧化镁，二氧化铈，氧化锌，氧化磷和包含两种或更多种这些氧化物的组合的复合氧化物，其中经受煅烧沸石的热处理包括煅烧，其中没有离子交换的沸石在350℃下进行热处理或更高温度在350℃至450℃的范围内加热。

8. 发明授权

US5550399A Integrated circuit with windowed fuse element and contact pad 失效
标题翻译：具有窗口保险丝元件和接触垫的集成电路
公开(公告)号：US5550399A
公开(公告)日：1996-08-27
申请号：US355387
申请日：1994-11-03
申请人： Motoya Okazaki
发明人： Motoya Okazaki
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L23/525 , H01L29/00
CPC分类号： H01L23/5256 , H01L24/05 , H01L2224/05553 , H01L2224/05567 , H01L2224/05624 , H01L2224/05666 , H01L2224/05684 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/12042 , H01L2924/14
摘要： A permanently alterable, i.e., customizable, integrated circuit has a fuse element and contact pad, and windows extending above the same through an insulative layer. The contact pad window extends down to and exposes the contact pad. The fuse element window terminates just short of the fuse element so that the fuse element remains covered by a thin layer of insulative material. The fuse element and the contact pad reside in a common plane of the substrate and thus can be formed together using a single photolithographic transfer step. Windows of different depth are created above the fuse element and contact pad in a single etching step by providing at least one narrow width etching pattern resist aperture above the fuse element. This slows the etch rate at the fused element relative to that at the contact pad, due to a microloading effect.
摘要翻译：永久可变的，即可定制的集成电路具有熔丝元件和接触焊盘，以及在其上延伸穿过绝缘层的窗户。接触垫窗口向下延伸并暴露接触垫。保险丝窗口终止于保险丝元件的短处，使得保险丝元件保持被薄的绝缘材料层覆盖。熔丝元件和接触垫位于基板的公共平面中，因此可以使用单个光刻转印步骤一起形成。通过在熔丝元件上方提供至少一个窄宽度的蚀刻图案抗蚀剂孔，在单个蚀刻步骤中在熔丝元件和接触焊盘上方形成不同深度的窗口。由于微负载效应，这使得熔融元件处的蚀刻速率相对于接触焊盘处的蚀刻速度变慢。

9. 发明申请

US20110270010A1 HYDROGENATION ISOMERIZATION CATALYST, METHOD FOR PRODUCING SAME, METHOD FOR DEWAXING HYDROCARBON OIL, AND METHOD FOR PRODUCING LUBRICANT BASE OIL 有权
标题翻译：氢化异构化催化剂，其生产方法，用于沥青油的方法和生产润滑油基础油的方法
公开(公告)号：US20110270010A1
公开(公告)日：2011-11-03
申请号：US13140144
申请日：2009-12-25
申请人： Kazuaki Hayasaka , Motoya Okazaki , Mayumi Yokoi
发明人： Kazuaki Hayasaka , Motoya Okazaki , Mayumi Yokoi
IPC分类号： B01J29/072 , C07C7/148
CPC分类号： C10M177/00 , B01J29/7261 , B01J29/7284 , B01J29/7292 , B01J29/7461 , B01J29/7484 , B01J29/7492 , B01J29/7861 , B01J29/7884 , B01J29/7892 , B01J35/002 , B01J37/0009 , B01J37/0201 , B01J2229/42 , C10G45/64 , C10G2300/1022 , C10G2300/1074 , C10G2300/1077 , C10G2400/10 , C10N2270/00
摘要： A first hydroisomerization catalyst contains a support being a extruded product prepared by calcination having a thermal treatment that includes thermally treating at 350° C. or more and at least one metal supported on the support and selected from the group consisting of metals belonging to Groups 8 to 10 of the periodic table, molybdenum and tungsten, wherein the support contains (a1) a calcined zeolite prepared by calcination having a thermal treatment that includes thermally treating at 350° C. or more of an ion-exchanged zeolite obtained by ion exchange of an organic template-containing zeolite containing an organic template and having a 10-membered ring one-dimensional porous structure in a solution containing ammonium ions and/or protons, and (b1) a calcined inorganic oxide prepared by calcination having a thermal treatment that includes thermally treating at 350° C. or more of one inorganic oxide selected from the group consisting of alumina, silica, titania, boria, zirconia, magnesia, ceria, zinc oxide, phosphorus oxide, and a composite oxide containing a combination of two or more of these oxides, wherein the thermal treatment to which the calcined zeolite has been subjected includes calcination in which the ion-exchanged zeolite that has not been thermally treated at 350° C. or more is heated within the range of 350° C. to 450° C.
摘要翻译：第一加氢异构化催化剂含有载体，其为通过煅烧制备的挤出产物，该热处理包括在350℃或更高温度下热处理和至少一种负载在载体上的金属，并且选自属于第8族的金属至（10）的元素周期表中的钼和钨，其中所述载体包含（a1）通过煅烧制备的煅烧沸石，其具有热处理，所述热处理包括在350℃或更高温度下热处理通过离子交换获得的离子交换沸石含有有机模板的沸石，含有有机模板，并且在含有铵离子和/或质子的溶液中具有10元环一维多孔结构，（b1）通过煅烧制备的煅烧无机氧化物，其具有热处理，所述热处理包括在350℃以上的一种无机氧化物热处理，其选自氧化铝，二氧化硅，二氧化钛，氧化硼，氧化锆，氧化镁，二氧化铈，氧化锌，氧化磷和包含两种或更多种这些氧化物的组合的复合氧化物，其中经受煅烧沸石的热处理包括煅烧，其中没有离子交换的沸石在350℃下进行热处理或更高温度在350℃至450℃的范围内加热。

10. 发明授权

US5874201A Dual damascene process having tapered vias 失效
标题翻译：双镶嵌工艺具有锥形通孔
公开(公告)号：US5874201A
公开(公告)日：1999-02-23
申请号：US461813
申请日：1995-06-05
申请人： Thomas John Licata , Ronald Wayne Nunes , Motoya Okazaki
发明人： Thomas John Licata , Ronald Wayne Nunes , Motoya Okazaki
IPC分类号： H01L23/538 , H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/768 , G03F7/26
CPC分类号： H01L21/76804 , H01L21/76807
摘要： A process for forming a dual-damascene interconnect employs a spun-on organic layer above an interlayer dielectric having a set of apertures for vias that forms tapered regions about the apertures without penetrating the apertures; the slope of the tapered regions being transferred in the etching process to form self-aligned tapered vias.
摘要翻译：用于形成双镶嵌互连的方法使用层间电介质上方的纺丝有机层，其具有用于通孔的一组孔，其围绕孔形成锥形区而不穿透孔; 锥形区域的斜率在蚀刻工艺中转移以形成自对准的锥形通孔。

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