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1. 发明申请

US20110196994A1 DMA CONTROL DEVICE AND DATA TRANSFER METHOD 审中-公开
标题翻译： DMA控制设备和数据传输方法
公开(公告)号：US20110196994A1
公开(公告)日：2011-08-11
申请号：US12675460
申请日：2008-08-12
申请人： Masaaki Harada , Tomohiko Kitamura , Tsutomu Sekibe
发明人： Masaaki Harada , Tomohiko Kitamura , Tsutomu Sekibe
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F21/85
摘要： A DMA control device and a data transfer method, which make it possible to use a DMA channel independent of an operation mode of a processor and realize the protection of DMA control parameters during DMA operation (during a data transfer), while reducing the number of shift of an operating mode of the processor as small as possible, are provided. In requesting a DMA start by locking an access to a ch-0 DMA control register 114 in a secure mode, a CPU 101 instructs an unlock set register 118 to release an access lock when the transfer is completed. Then, when a parameter controlling circuit 119 receives a notification of transfer completion from a ch-0 state managing circuit 116, such parameter controlling circuit instructs a lock set register 115 to release the lock in accordance with the setting of the unlock set register 118.
摘要翻译：一种DMA控制装置和数据传输方法，其可以独立于处理器的操作模式使用DMA通道，并且在DMA操作期间（在数据传输期间）实现对DMA控制参数的保护，同时减少提供了尽可能小的处理器的操作模式的移动。在通过在安全模式下锁定对ch-0 DMA控制寄存器114的访问来请求DMA开始时，CPU 101指示解锁设置寄存器118在传送完成时释放访问锁定。然后，当参数控制电路119从ch-0状态管理电路116接收到传送完成的通知时，该参数控制电路根据解锁设定寄存器118的设定指示锁定设定寄存器115释放锁定。

2. 发明授权

US06225916B1 Remote control signal reception controller 失效
标题翻译：遥控信号接收控制器
公开(公告)号：US06225916B1
公开(公告)日：2001-05-01
申请号：US09127376
申请日：1998-07-31
申请人： Hiroko Sugimoto , Tsutomu Sekibe , Hideyuki Kanzaki , Tomohiko Kitamura
发明人： Hiroko Sugimoto , Tsutomu Sekibe , Hideyuki Kanzaki , Tomohiko Kitamura
IPC分类号： H04Q700
CPC分类号： G08C19/28 , G08C25/00
摘要： The remote control signal reception controller receives control data transmitted from a remote control signal sender. The remote control signal reception controller informs a CPU that controls a device of the information on the received control data by interrupting the CPU. When doing so, the remote control signal reception controller judges whether a piece of control data that has just been received and a preceding piece of control data were consecutively transmitted, and whether these two pieces of control data are the same control data. The remote control signal reception controller interrupts the CPU only once when finding that the same control data is continuously transmitted as the result of this judgement.
摘要翻译：遥控信号接收控制器接收从遥控信号发送器发送的控制数据。遥控信号接收控制器通过中断CPU来通知CPU控制所接收的控制数据的信息的装置。当这样做时，遥控信号接收控制器判断是否连续发送了刚刚接收到的一条控制数据和前一条控制数据，以及这两条控制数据是否是相同的控制数据。作为判断结果，当发现连续发送相同的控制数据时，遥控信号接收控制器仅中断CPU一次。

3. 发明授权

US5579500A Control apparatus for controlling data read accesses to memory and subsequent address generation scheme based on data/memory width determination and address validation 失效
标题翻译：用于基于数据/存储器宽度确定和地址确认来控制对存储器的数据读取访问和后续地址生成方案的控制装置
公开(公告)号：US5579500A
公开(公告)日：1996-11-26
申请号：US200217
申请日：1994-02-23
申请人： Tsutomu Sekibe , Tomohiko Kitamura , Toshiyuki Ochiai
发明人： Tsutomu Sekibe , Tomohiko Kitamura , Toshiyuki Ochiai
IPC分类号： G06F12/02
CPC分类号： G06F12/0215
摘要： An apparatus and method for controlling data read access to memory, in response to an access request sent through a system bus. The apparatus includes an data storage device for preserving data corresponding to a predetermined address; a judging device for judging whether an access address indicated by the access request matches the predetermined address; and a control device for making the data storage device output data preserved therein to the system bus when the access address has been judged to match the predetermined address, and for making the data storage device hold data corresponding to a next address subsequent to the access address when the access address has been judged not to match the predetermined address.
摘要翻译：响应于通过系统总线发送的访问请求，控制对存储器的数据读取访问的装置和方法。该装置包括用于保存对应于预定地址的数据的数据存储装置; 用于判断由所述访问请求指示的访问地址是否匹配所述预定地址的判断装置; 以及控制装置，用于当访问地址已经被判定为与预定地址相匹配时，用于使数据存储装置输出保存在其中的数据到系统总线，并且使得数据存储装置保持对应于访问地址之后的下一个地址的数据当访问地址被判定为不符合预定地址时。

4. 发明授权

US06804742B1 System integrated circuit 失效
标题翻译：系统集成电路
公开(公告)号：US06804742B1
公开(公告)日：2004-10-12
申请号：US09711432
申请日：2000-11-13
申请人： Tomohiko Kitamura , Masataka Osaka , Tsutomu Sekibe
发明人： Tomohiko Kitamura , Masataka Osaka , Tsutomu Sekibe
IPC分类号： G06F1336
CPC分类号： G06F11/366 , G06F11/364 , G06F11/3648
摘要： A system integrated circuit that identifies the cause of a malfunction even if the number of output terminals of a system LSI to be assigned to internal buses in the system LSI is strictly restricted. Comparators 11 to 15 are connected to any of a plurality of buses. Each comparator judges whether a certain expected value matches data transferred on a bus connected to the comparator. The selector unit 10 selects one of the plurality of buses in accordance with the judgement result of the comparator, and outputs data transferred on the selected bus to outside the system integrated circuit so that an observer can observe internal state of the system integrated circuit from outside.
摘要翻译：即使系统LSI中分配给内部总线的系统LSI的输出端子数量受到严格限制，也能够识别故障原因的系统集成电路。比较器11至15连接到多个总线中的任一个。每个比较器判断某个预期值是否匹配与连接到比较器的总线上传输的数据。选择器单元10根据比较器的判断结果选择多个总线中的一个，并将在所选择的总线上传送的数据输出到系统集成电路外部，使得观察者可以从外部观察系统集成电路的内部状态。

5. 发明授权

US06477606B1 Bus system and a master device that stabilizes bus electric potential during non-access periods 有权
标题翻译：总线系统和主设备，可在非访问期间稳定总线电位
公开(公告)号：US06477606B1
公开(公告)日：2002-11-05
申请号：US09378548
申请日：1999-08-20
申请人： Osamu Kawamura , Tomohiko Kitamura , Tsutomu Sekibe
发明人： Osamu Kawamura , Tomohiko Kitamura , Tsutomu Sekibe
IPC分类号： G06F1314
CPC分类号： G06F13/423 , Y02D10/14 , Y02D10/151
摘要： A master device in a system including a bidirectional bus and at least one device manages whether the system is in an access state in which the master device permits an access to or from one device or a non-access state in which the master device permits an access to none of the devices. The master device drives the bidirectional bus using a predetermined current to transfer data to or from one device connected to the bidirectional bus when the system is in the access state. When the state of the system changes from the access state to the non-access state, the master device drives the bidirectional bus in order to stabilize the potential of the bidirectional bus to keep the bus potential from changing when the system is in a non-access state, thereby eliminating the need for conventional pull-up/pull-down resistors for stabilizing the bus potential during a non-access state.
摘要翻译：包括双向总线和至少一个设备的系统中的主设备管理系统是否处于主设备允许接入或来自一个设备的接入状态或主设备允许的非接入状态无法访问任何设备。当系统处于访问状态时，主设备使用预定的电流来驱动双向总线，以将数据传送到连接到双向总线的一个设备。当系统的状态从访问状态变为非访问状态时，主设备驱动双向总线，以便稳定双向总线的电位，以便在系统处于非接入状态时保持总线电位不变，从而消除了在非访问状态期间稳定总线电位的常规上拉/下拉电阻的需要。

6. 发明授权

US06633926B1 DMA transfer device capable of high-speed consecutive access to pages in a memory 有权
标题翻译： DMA传输设备能够高速连续访问存储器中的页面
公开(公告)号：US06633926B1
公开(公告)日：2003-10-14
申请号：US09450873
申请日：1999-11-29
申请人： Masaaki Harada , Tsutomu Sekibe
发明人： Masaaki Harada , Tsutomu Sekibe
IPC分类号： G06F1300
CPC分类号： G06F13/28
摘要： A DMA transfer device transfers data from a first region to a second region in a memory allowing high-speed page access. The DMA transfer device includes: a first detecting unit for detecting a plurality of read areas that form the first region, each read area being located between page boundaries; a second detecting unit for detecting a plurality of write areas that form the second region, each write area being located between page boundaries; and an access unit for performing high-speed page access to each of the read areas and each of the write areas.
摘要翻译： DMA传输设备将数据从第一区域传送到允许高速页面访问的存储器中的第二区域。 DMA传送装置包括：第一检测单元，用于检测形成第一区域的多个读取区域，每个读取区域位于页面边界之间; 第二检测单元，用于检测形成第二区域的多个写入区域，每个写入区域位于页面边界之间; 以及用于对每个读取区域和每个写入区域执行高速页面访问的访问单元。

7. 发明授权

US07793083B2 Processor and system for selectively disabling secure data on a switch 有权
标题翻译：处理器和系统，用于选择性地禁用交换机上的安全数据
公开(公告)号：US07793083B2
公开(公告)日：2010-09-07
申请号：US11667762
申请日：2005-11-24
申请人： Masaaki Harada , Tsutomu Sekibe
发明人： Masaaki Harada , Tsutomu Sekibe
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F12/0891 , G06F12/14 , G06F12/1491 , G06F21/10 , G06F21/105 , G06F21/6227 , G06F21/79 , G06F21/85 , G06F2221/2105 , G06F2221/2137
摘要： A processor (10) manages, in an instruction management unit (103) and a data attribute management unit (105), secure attributes indicating whether instruction code and data stored in an instruction cache (102) and a data cache (104) of the processor (10) are confidential information. When the instruction code and the data are confidential information, the processor (10) also manages secure processing identification information for indicating in which secure process the confidential information is to be used. When the operating mode is switched from the secure mode to the normal mode, only the confidential information is disabled by a memory disabling unit (108). This prevents confidential information from being analyzed by the processor in the normal mode.
摘要翻译：处理器（10）在指令管理单元（103）和数据属性管理单元（105）中管理指示存储在指令高速缓存（102）和数据高速缓存（104）中的指令代码和数据的安全属性处理器（10）是机密信息。当指令代码和数据是机密信息时，处理器（10）还管理安全处理识别信息，用于指示在哪个安全处理中使用机密信息。当操作模式从安全模式切换到正常模式时，只有秘密信息被存储器禁用单元（108）禁用。这防止在正常模式下由处理器分析机密信息。

8. 发明申请

US20080052534A1 Processor and Secure Processing System 有权
标题翻译：处理器和安全处理系统
公开(公告)号：US20080052534A1
公开(公告)日：2008-02-28
申请号：US11667762
申请日：2005-11-24
申请人： Masaaki Harada , Tsutomu Sekibe
发明人： Masaaki Harada , Tsutomu Sekibe
IPC分类号： G06F12/14
CPC分类号： G06F12/0891 , G06F12/14 , G06F12/1491 , G06F21/10 , G06F21/105 , G06F21/6227 , G06F21/79 , G06F21/85 , G06F2221/2105 , G06F2221/2137
摘要： A processor (10) manages, in an instruction management unit (103) and a data attribute management unit (105), secure attributes indicating whether instruction code and data stored in an instruction cache (102) and a data cache (104) of the processor (10) are confidential information. When the instruction code and the data are confidential information, the processor (10) also manages secure processing identification information for indicating in which secure process the confidential information is to be used. When the operating mode is switched from the secure mode to the normal mode, only the confidential information is disabled by a memory disabling unit (108). This prevents confidential information from being analyzed by the processor in the normal mode.
摘要翻译：处理器（10）在指令管理单元（103）和数据属性管理单元（105）中管理指示存储在指令高速缓存（102）和数据高速缓存（104）中的指令代码和数据的安全属性处理器（10）是机密信息。当指令代码和数据是机密信息时，处理器（10）还管理安全处理识别信息，用于指示在哪个安全处理中使用机密信息。当操作模式从安全模式切换到正常模式时，只有秘密信息被存储器禁用单元（108）禁用。这防止在正常模式下由处理器分析机密信息。

9. 发明授权

US08693379B2 Communication system, communication device, and communication method 有权
标题翻译：通信系统，通信设备和通信方式
公开(公告)号：US08693379B2
公开(公告)日：2014-04-08
申请号：US12676433
申请日：2009-07-21
申请人： Shinichiro Nishioka , Tsutomu Sekibe
发明人： Shinichiro Nishioka , Tsutomu Sekibe
IPC分类号： H04L5/16
CPC分类号： H04L5/14 , H04L5/16
摘要： A communication system performs communication while switching between full-duplex communication and half-duplex communication. A slave device, which receives command packet signals requesting to write or read data from the master device, stores information in a response packet signal that specifies half-duplex communication in response to one of the received packet signals, and transmits the response packet signal to the master device, when the number of the received command packet signals has reached the maximum number of the command packet signals storable in a command signal queue.
摘要翻译：通信系统在全双工通信和半双工通信之间切换时进行通信。接收请求从主设备写入或读取数据的命令分组信号的从设备响应于所接收的分组信号之一将信息存储在指定半双工通信的响应分组信号中，并将响应分组信号发送到当接收到的命令分组信号的数量已经达到可存储在命令信号队列中的命令分组信号的最大数量时，主设备。

10. 发明授权

US08351356B2 Data communication system, communication device, and communication method 有权
标题翻译：数据通信系统，通信设备和通信方式
公开(公告)号：US08351356B2
公开(公告)日：2013-01-08
申请号：US12674045
申请日：2009-06-11
申请人： Shinichiro Nishioka , Hiroshi Suenaga , Tsutomu Sekibe , Isao Kato , Tadashi Ono , Hideyuki Yamada
发明人： Shinichiro Nishioka , Hiroshi Suenaga , Tsutomu Sekibe , Isao Kato , Tadashi Ono , Hideyuki Yamada
IPC分类号： H04L5/16 , H04L5/14 , G06F13/12
CPC分类号： H04L25/0272 , H04L5/14 , H04L5/1438 , H04L5/16
摘要： A data communication system for starting transmission and reception of target data for processing upon recognition that switching between communication modes is completed. The data communication system includes a master communication device and a slave communication device that continuously perform, at a time of switching from half-duplex communication to full-duplex communication, (i) a handshake using a directional control code indicating the switching and a preamble code indicating completion of the switching and (ii) a handshake using the preamble code and an acknowledge code indicating receipt of the preamble code, whereby each of the devices recognizes that the switching between communication modes by the opposite device is completed and starts transmission and reception of the target data.
摘要翻译：一种数据通信系统，用于在识别出完成通信模式之间的切换的情况下开始用于处理的目标数据的发送和接收。数据通信系统包括在从半双工通信切换到全双工通信时连续执行主通信设备和从通信设备，（i）使用指示切换的方向控制代码的握手和前导码指示切换完成的代码和（ii）使用前导码的握手和指示接收前导码的确认代码，由此每个设备识别出相对设备的通信模式之间的切换完成并开始发送和接收的目标数据。

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