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    • 2. 发明申请
    • MEMORY EFFECT REDUCTION USING LOW IMPEDANCE BIASING
    • 使用低阻抗偏移的存储器效应减少
    • WO2015066704A1
    • 2015-05-07
    • PCT/US2014/063912
    • 2014-11-04
    • MARVELL WORLD TRADE, LTD.
    • SIGNOFF, David, M.HE, MingLOEB, Wayne, A.
    • H03F1/32H03F1/30
    • H03F3/245G05F1/46H03F1/301H03F1/308H03F3/195H03F3/265H03F3/505H03F2200/24H03F2200/451H03F2200/453H03F2200/534H03F2200/555H03F2200/69H03H7/0107
    • A circuit includes a bias circuit for a biased transistor. The bias circuit includes a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to the biased transistor and configured to provide a bias voltage. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. A signal ground circuit may be coupled between the biased transistor and one or more components of the bias circuit that do not generate significant return currents to a power supply ground. A method includes generating a current in a reference transistor according to a first voltage generated using a master source follower circuit, generating a second voltage substantially identical to the first voltage using a slave source follower circuit, and providing the second voltage to a biased transistor. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor.
    • 电路包括用于偏置晶体管的偏置电路。 偏置电路包括主从源极跟随器电路,参考晶体管和耦合到偏置晶体管并被配置为提供偏置电压的偏置电路电压输出。 参考晶体管具有与偏置晶体管的跨导基本相同的跨导。 信号接地电路可以耦合在偏置晶体管和偏置电路的一个或多个组件之间,其不产生到电源接地的大的返回电流。 一种方法包括根据使用主源跟随器电路产生的第一电压产生参考晶体管中的电流,使用从源跟随器电路产生与第一电压基本相同的第二电压,以及将第二电压提供给偏置晶体管。 参考晶体管具有与偏置晶体管的跨导基本相同的跨导。