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1. 发明申请

US20090146691A1 LOGIC CELL ARRAY AND BUS SYSTEM 有权
标题翻译：逻辑单元阵列和总线系统
公开(公告)号：US20090146691A1
公开(公告)日：2009-06-11
申请号：US12371040
申请日：2009-02-13
申请人： Martin VORBACH , Frank MAY , Dirk REICHARDT , Frank LIER , Gerd EHLERS , Armin NUCKEL , Volker BAUMGARTE , Prashant RAO , Jens OERTEL
发明人： Martin VORBACH , Frank MAY , Dirk REICHARDT , Frank LIER , Gerd EHLERS , Armin NUCKEL , Volker BAUMGARTE , Prashant RAO , Jens OERTEL
IPC分类号： H03K19/177 , G06F7/52 , G06F15/00
CPC分类号： G06F13/4027 , G06F9/3001 , G06F13/4022 , G06F15/7825 , G06F15/7867 , G06F15/80 , G06F15/8023 , G06F15/8092 , G06F15/82 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.
摘要翻译：具有多个逻辑单元的逻辑单元阵列和用于逻辑单元通信的分段总线系统，所述总线系统包括具有较短和较长段的不同段线，用于连接两个点，以便能够最小化在单独的通信开始和结束点。

2. 发明申请

US20100070671A1 METHOD AND DEVICE FOR PROCESSING DATA 有权
标题翻译：用于处理数据的方法和设备
公开(公告)号：US20100070671A1
公开(公告)日：2010-03-18
申请号：US12621860
申请日：2009-11-19
申请人： Martin VORBACH , Frank May , Armin Nuckel
发明人： Martin VORBACH , Frank May , Armin Nuckel
IPC分类号： G06F13/14
CPC分类号： G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： In a system including a multidimensional field of reconfigurable elements, and a method for operating said field of reconfigurable elements, one or more groups of said elements suitable for processing a predetermined task may be determined, a particular one of the one or more groups is selected, and the selected group is configured in a predetermined manner during runtime for processing the predetermined task, and in manufacturing of said system.
摘要翻译：在包括可重构元件的多维场的系统以及用于操作所述可重构元件的场的方法中，可以确定适于处理预定任务的一个或多个所述元件组，选择一个或多个组中的特定一个组，并且在运行时间期间以预定方式配置所选择的组以处理预定任务，以及在所述系统的制造中。

3. 发明申请

US20120072699A1 LOGIC CELL ARRAY AND BUS SYSTEM 有权
标题翻译：逻辑单元阵列和总线系统
公开(公告)号：US20120072699A1
公开(公告)日：2012-03-22
申请号：US13289296
申请日：2011-11-04
申请人： Martin VORBACH , Frank May , Dirk Reichardt , Frank Lier , Gerd Ehlers , Armin Nückel , Volker Baumgarte , Prashant Rao , Jens Oertel
发明人： Martin VORBACH , Frank May , Dirk Reichardt , Frank Lier , Gerd Ehlers , Armin Nückel , Volker Baumgarte , Prashant Rao , Jens Oertel
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F13/4027 , G06F9/3001 , G06F13/4022 , G06F15/7825 , G06F15/7867 , G06F15/80 , G06F15/8023 , G06F15/8092 , G06F15/82 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.
摘要翻译：具有多个逻辑单元的逻辑单元阵列和用于逻辑单元通信的分段总线系统，所述总线系统包括具有较短和较长段的不同段线，用于连接两个点，以便能够最小化在单独的通信开始和结束点。

4. 发明申请

US20100095094A1 METHOD FOR PROCESSING DATA 审中-公开
标题翻译：数据处理方法
公开(公告)号：US20100095094A1
公开(公告)日：2010-04-15
申请号：US12640201
申请日：2009-12-17
申请人： Martin VORBACH , Armin Nückel , Frank May , Markus Weinhardt , Joao Manuel Paiva Cardoso
发明人： Martin VORBACH , Armin Nückel , Frank May , Markus Weinhardt , Joao Manuel Paiva Cardoso
IPC分类号： G06F9/30
CPC分类号： G06F8/45 , G06F15/7867
摘要： A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first processor.
摘要翻译：一种用于将程序转换为包括至少一个第一处理器和可重构单元的系统的方法和装置。确定适合于可重构单元的程序的代码部分。程序的剩余代码被提取和/或分离以供第一处理器处理。

5. 发明申请

US20120311301A1 PIPELINE CONFIGURATION PROTOCOL AND CONFIGURATION UNIT COMMUNICATION 有权
标题翻译：管道配置协议和配置单元通信
公开(公告)号：US20120311301A1
公开(公告)日：2012-12-06
申请号：US13491894
申请日：2012-06-08
申请人： Martin VORBACH , Volker Baumgarte , Gerd Ehlers , Frank May , Armin Nückel
发明人： Martin VORBACH , Volker Baumgarte , Gerd Ehlers , Frank May , Armin Nückel
IPC分类号： G06F15/76
CPC分类号： G06F15/7867 , G06F9/3885 , G06F9/3897
摘要： In a method of synchronizing data processing of processor arrangement, responsive to reaching, during execution of a program, a barrier included in a program sequence, the processor arrangement halts the program execution until it is determined that all instructions preceding the barrier in the program sequence have been successfully scheduled for execution.
摘要翻译：在一种使处理器装置的数据处理同步的方法中，响应于在程序执行期间到达包括在程序序列中的屏障，处理器装置停止程序执行，直到确定程序序列中的屏障之前的所有指令已经成功安排执行。

6. 发明申请

US20120278772A1 HARDWARE DEFINITION METHOD INCLUDING DETERMINING WHETHER TO IMPLEMENT A FUNCTION AS HARDWARE OR SOFTWARE 审中-公开
标题翻译：硬件定义方法，包括确定实现作为硬件或软件的功能
公开(公告)号：US20120278772A1
公开(公告)日：2012-11-01
申请号：US13491935
申请日：2012-06-08
申请人： Martin VORBACH , Frank MAY
发明人： Martin VORBACH , Frank MAY
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5054
摘要： A hardware definition system and method includes a computer processor analyzing software function modules of a software program, and generating, for each of at least a subset of the software function modules, and on the basis of the analyzing step, a respective setting indicating whether the respective function module is to be implemented as a respective hardware module or as a software module executed on a hardware module defined in a hardware module library.
摘要翻译：硬件定义系统和方法包括：计算机处理器，对软件程序的软件功能模块进行分析，并且对软件功能模块的至少一个子集中的每个软件功能模块进行分析，并且基于分析步骤，相应的功能模块将被实现为相应的硬件模块或作为在硬件模块库中定义的硬件模块上执行的软件模块。

7. 发明申请

US20110271264A1 METHOD FOR THE TRANSLATION OF PROGRAMS FOR RECONFIGURABLE ARCHITECTURES 有权
标题翻译：翻译可重构建筑方案的方法
公开(公告)号：US20110271264A1
公开(公告)日：2011-11-03
申请号：US13177820
申请日：2011-07-07
申请人： Martin VORBACH , Frank May , Armin Nückel
发明人： Martin VORBACH , Frank May , Armin Nückel
IPC分类号： G06F9/45
CPC分类号： G06F8/447
摘要： Data processing using multidimensional fields is described along with methods for advantageously using high-level language codes.
摘要翻译：描述使用多维字段的数据处理以及有利地使用高级语言代码的方法。

8. 发明申请

US20120151113A1 BUS SYSTEMS AND METHODS FOR CONTROLLING DATA FLOW IN A FIELD OF PROCESSING ELEMENTS 审中-公开
标题翻译：用于控制处理元件的数据流的总线系统和方法
公开(公告)号：US20120151113A1
公开(公告)日：2012-06-14
申请号：US13324048
申请日：2011-12-13
申请人： Martin VORBACH , Volker Baumgarte , Gerd Ehlers
发明人： Martin VORBACH , Volker Baumgarte , Gerd Ehlers
IPC分类号： G06F13/14
CPC分类号： G06F13/4068 , G06F15/7867
摘要： A bus system for a configurable architecture and methods therefor are provided in which optimization of the configuration efficiency and reconfiguration efficiency are taken into account separately. A system and method may include controlling data transmission by: transmitting, by a first hardware element and to a second hardware element, a data packet conditional upon and/or responsive to the second hardware element's assignment of a signal to a connecting bus via which the data packet is transmitted, where the signal indicates that no incoming data packet can be lost. A system and method may include controlling data transmission by: transmitting, by a first hardware element and to a second hardware element, a first data packet and subsequently a second data packet; and receiving, by the first hardware element and from the second hardware element, an acknowledgement of the first data packet subsequent to the transmittal of the second data packet.
摘要翻译：提供了一种用于可配置架构及其方法的总线系统，其中分别考虑了配置效率和重新配置效率的优化。系统和方法可以包括：通过以下步骤来控制数据传输：由第一硬件元件和第二硬件元件发送数据分组，该数据分组是有条件的和/或响应于第二硬件元件分配给连接总线的信号，发送数据包，其中该信号指示不丢失输入数据分组。系统和方法可以包括：通过以下步骤来控制数据传输：由第一硬件元件和第二硬件元件发送第一数据分组和随后的第二数据分组; 以及由所述第一硬件元件和所述第二硬件元件接收在所述第二数据分组的发送之后的所述第一数据分组的确认。

9. 发明申请

US20110148460A1 RECONFIGURABLE SEQUENCER STRUCTURE 有权
公开(公告)号：US20110148460A1
公开(公告)日：2011-06-23
申请号：US13040769
申请日：2011-03-04
申请人： Martin VORBACH
发明人： Martin VORBACH
IPC分类号： H03K19/173
CPC分类号： G06F15/7867 , G06F9/30145 , G06F13/16 , G06F13/36 , G06F13/4068 , H03K19/173
摘要： A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory cell means.

10. 发明申请

US20090153188A1 PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPs) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAs, DPGAs AND THE LIKE) 审中-公开
标题翻译：数据流处理器（DFP）的自动动态过程和具有两维或三维可编程细胞结构（FPGA，DPGAs和类似）的单元的过程
公开(公告)号：US20090153188A1
公开(公告)日：2009-06-18
申请号：US12389155
申请日：2009-02-19
申请人： Martin VORBACH , Robert MUNCH
发明人： Martin VORBACH , Robert MUNCH
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： G06F15/7867 , G06F9/30
摘要： In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.
摘要翻译：在数据处理方法中，可以使用多个可配置的粗粒度元素来获得第一结果数据，第一结果数据可以被写入到包括空间上分离的第一和第二存储器区域并且经由总线连接到可以随后从存储器中读出多个可配置的粗粒度元素，第一结果数据可以随后使用多个可配置的粗粒度元素进行处理。在第一配置中，第一存储器区域可以被配置为写入存储器，并且第二存储器区域可以被配置为读取存储器。在根据第一配置写入和读取存储器之后，第一存储器区域可以被配置为读取存储器，并且第二存储器区域可以被配置为写入存储器。

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