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1. 发明授权

US5331164A Particle sensor array 失效
标题翻译：粒子传感器阵列
公开(公告)号：US5331164A
公开(公告)日：1994-07-19
申请号：US672705
申请日：1991-03-19
申请人： Martin G. Buehler , Brent R. Blaes , Udo Lieneweg
发明人： Martin G. Buehler , Brent R. Blaes , Udo Lieneweg
IPC分类号： G01T1/24 , G11C11/412 , H01L27/11 , H01L27/146 , H01L31/119 , H01L29/78
CPC分类号： G01T1/245 , G11C11/4125 , H01L27/1104 , H01L27/146 , H01L31/119
摘要： A particle sensor array which in a preferred embodiment comprises a static random access memory having a plurality of ion-sensitive memory cells, each such cell comprising at least one pull-down field effect transistor having a sensitive drain surface area (such as by bloating) and at least one pull-up field effect transistor having a source connected to an offset voltage. The sensitive drain surface area and the offset voltage are selected for memory cell upset by incident ions such as alpha-particles. The static random access memory of the present invention provides a means for selectively biasing the memory cells into the same state in which each of the sensitive drain surface areas is reverse biased and then selectively reducing the reversed bias on these sensitive drain surface areas for increasing the upset sensitivity of the cells to ions. The resulting selectively sensitive memory cells can be used in a number of applications. By way of example, the present invention can be used for measuring the linear energy transfer of ion particles, as well as a device for assessing the resistance of CMOS latches to Cosmic Ray induced single event upsets. The sensor of the present invention can also be used to determine the uniformity of an ion beam.
摘要翻译：在优选实施例中的粒子传感器阵列包括具有多个离子敏感存储器单元的静态随机存取存储器，每个这样的单元包括至少一个下拉场效应晶体管，其具有敏感的漏极表面积（例如通过膨胀）以及具有连接到偏移电压的源极的至少一个上拉场效应晶体管。选择敏感的漏极表面积和偏移电压用于由诸如α粒子的入射离子引起的存储器单元的镦粗。本发明的静态随机存取存储器提供了一种用于选择性地将存储单元偏置成相同状态的装置，其中每个敏感漏极表面区域被反向偏置，然后选择性地减小这些敏感漏极表面区域上的反向偏置，以增加细胞对离子的不适灵敏度。所产生的选择敏感的存储器单元可用于许多应用中。作为示例，本发明可以用于测量离子颗粒的线性能量传递，以及用于评估CMOS锁存器对宇宙射线诱发的单事件扰动的电阻的装置。本发明的传感器也可用于确定离子束的均匀性。

2. 发明授权

US4688947A Method and apparatus for characterizing propagation delays of integrated circuit devices 失效
标题翻译：表征集成电路器件的传播延迟的方法和装置
公开(公告)号：US4688947A
公开(公告)日：1987-08-25
申请号：US829772
申请日：1986-02-18
申请人： Brent R. Blaes , Martin G. Buehler
发明人： Brent R. Blaes , Martin G. Buehler
IPC分类号： G01R31/317 , G01R31/3193 , G04F10/00 , G04F8/00
CPC分类号： G04F10/00 , G01R31/31725 , G01R31/31937
摘要： Propagation delay of a signal through a channel is measured by cyclically generating a first step-wave signal for transmission through the channel to a two-input logic element and a second step-wave signal with a controlled delay to the second input terminal of the logic element. The logic element determines which signal is present first at its input terminals and stores a binary signal indicative of that determination for control of the delay of the second signal which is advanced or retarded for the next cycle until both the propagation delayed first step-wave signal and the control delayed step-wave signal are coincident. The propagation delay of the channel is then determined by measuring the time between the first and second step-wave signals out of the controlled step-wave signal generator.
摘要翻译：通过频道的信号的传播延迟通过循环产生第一步波信号来测量，以通过信道传输到双输入逻辑元件和具有受控延迟的第二步波信号到逻辑的第二输入端元件。逻辑元件确定哪个信号首先存在于其输入端，并且存储指示该决定的二进制信号，用于控制下一个周期中先进或延迟的第二信号的延迟，直到传播延迟的第一阶跃波信号并且控制延迟阶跃波信号一致。然后通过测量受控步进波信号发生器之间的第一和第二步波信号之间的时间来确定通道的传播延迟。

3. 发明授权

US5753920A Integrated charge monitor 失效
标题翻译：集成充电监视器
公开(公告)号：US5753920A
公开(公告)日：1998-05-19
申请号：US507527
申请日：1995-07-26
申请人： Martin G. Buehler , Brent R. Blaes , George A. Soli
发明人： Martin G. Buehler , Brent R. Blaes , George A. Soli
IPC分类号： G01T1/02 , G01T1/24
CPC分类号： G01T1/02 , G01T1/24 , G01T1/247
摘要： An integrated charge monitor for measuring a level of cumulative radiation exposure includes semiconductor devices having characteristics that change with a cumulative level of radiation to which the devices are exposed, different amounts of radiation shielding associated with each of the devices, and circuitry operable to separately address each of the devices to measure a change in the characteristic of the selected device due to radiation exposure. The monitor may be implemented on a single integrated circuit chip. The monitor may also be employed in performing a spectrometric analysis of radiation based on the affect of the radiation on characteristics of multiple, differently-shielded semiconductor devices.
摘要翻译：用于测量累积辐射暴露水平的集成电荷监视器包括具有随设备暴露于的累积辐射水平而变化的特性的半导体器件，与每个器件相关联的不同数量的辐射屏蔽以及可操作以单独寻址的电路用于测量由于辐射暴露而导致的所选择的设备的特性变化的每个设备。监视器可以在单个集成电路芯片上实现。基于辐射对多个不同屏蔽的半导体器件的特性的影响，也可以使用监视器进行辐射的光谱分析。

4. 发明授权

US5396169A Method for characterizing the upset response of CMOS circuits using alpha-particle sensitive test circuits 失效
标题翻译：使用α粒子敏感测试电路来表征CMOS电路的不平衡响应的方法
公开(公告)号：US5396169A
公开(公告)日：1995-03-07
申请号：US956252
申请日：1992-10-05
申请人： Martin G. Buehler , Brent R. Blaes , Robert H. Nixon , George A. Soli
发明人： Martin G. Buehler , Brent R. Blaes , Robert H. Nixon , George A. Soli
IPC分类号： G01T1/24 , G11C11/412 , H01L27/11 , H01L27/146 , H01L31/119 , G01R1/04
CPC分类号： G01T1/245 , G11C11/4125 , H01L27/1104 , H01L27/146 , H01L31/119
摘要： A method for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. A technique utilizing test structures to quickly and inexpensively characterize the SEU sensitivity of standard cell latches intended for use in a space environment. This bench-level approach utilizes alpha particles to induce upsets in a low LET sensitive 4-k bit test SRAM. This SRAM consists of cells that employ an offset voltage to adjust their upset sensitivity and an enlarged sensitive drain junction to enhance the cell's upset rate.
摘要翻译：一种使用α粒子敏感SRAM，SPICE临界电荷模拟结果和α粒子相互作用物理学来预测标准单元D锁存器的SEU敏感性的方法。一种利用测试结构快速，低成本地表征用于空间环境的标准单元锁存器的SEU灵敏度的技术。这种台式方法利用α粒子在低LET敏感的4-k位测试SRAM中引起扰动。该SRAM由使用偏移电压来调节其镦粗灵敏度的单元和扩大的敏感漏极结以增强电池的镦粗率。

5. 发明授权

US5332903A p-MOSFET total dose dosimeter 失效
标题翻译： p-MOSFET总剂量计
公开(公告)号：US5332903A
公开(公告)日：1994-07-26
申请号：US983380
申请日：1992-11-30
申请人： Martin G. Buehler , Brent R. Blaes
发明人： Martin G. Buehler , Brent R. Blaes
IPC分类号： G01T1/24 , G11C11/412 , H01L27/11 , H01L27/146 , H01L31/119
CPC分类号： H01L27/1104 , G01T1/026 , G01T1/245 , G11C11/4125 , H01L27/146 , H01L31/119
摘要： A p-MOSFET total dose dosimeter where the gate voltage is proportional to the incident radiation dose. It is configured in an n-WELL of a p-BODY substrate. It is operated in the saturation region which is ensured by connecting the gate to the drain. The n-well is connected to zero bias. Current flow from source to drain, rather than from peripheral leakage, is ensured by configuring the device as an edgeless MOSFET where the source completely surrounds the drain. The drain junction is the only junction not connected to zero bias. The MOSFET is connected as part of the feedback loop of an operational amplifier. The operational amplifier holds the drain current fixed at a level which minimizes temperature dependence and also fixes the drain voltage. The sensitivity to radiation is made maximum by operating the MOSFET in the OFF state during radiation soak.
摘要翻译： p-MOSFET总剂量计，其中栅极电压与入射辐射剂量成比例。它被配置在p-BODY衬底的n-WELL中。它通过将栅极连接到漏极来确保饱和区域中运行。 n阱连接到零偏置。通过将器件配置为无源MOSFET，其源头完全包围漏极，确保了从源极到漏极而不是外围漏电流。漏极结是唯一没有连接到零偏置的结。 MOSFET作为运算放大器的反馈环路的一部分连接。运算放大器将漏极电流固定在使温度依赖性最小化的水平，并固定漏极电压。通过在辐射浸泡期间将MOSFET处于OFF状态，使对辐射的敏感度最大化。

6. 发明授权

US4719411A Addressable test matrix for measuring analog transfer characteristics of test elements used for integrated process control and device evaluation 失效
标题翻译：用于测量用于集成过程控制和设备评估的测试元件的模拟传输特性的可寻址测试矩阵
公开(公告)号：US4719411A
公开(公告)日：1988-01-12
申请号：US733110
申请日：1985-05-13
申请人： Martin G. Buehler
发明人： Martin G. Buehler
IPC分类号： G01R31/30 , G11C29/02 , G01R31/28
CPC分类号： G11C29/02 , G01R31/30
摘要： A set of addressable test structures, each of which uses addressing schemes to access individual elements of the structure in a matrix, is used to test the quality of a wafer before integrated circuits produced thereon are diced, packaged and subjected to final testing. The electrical characteristic of each element is checked and compared to the electrical characteristic of all other like elements in the matrix. The effectiveness of the addressable test matrix is in readily analyzing the electrical characteristics of the test elements and in providing diagnostic information.
摘要翻译：使用一组可寻址的测试结构，每个测试结构使用寻址方案来访问矩阵中的结构的各个元素，以便在其上生产的集成电路被切割，封装并进行最终测试之前测试晶片的质量。检查每个元件的电特性并将其与矩阵中所有其它相似元件的电特性进行比较。可寻址测试矩阵的有效性在于容易地分析测试元件的电气特性并提供诊断信息。

7. 发明授权

US06730201B1 Electronic tongue 失效
标题翻译：电子舌头
公开(公告)号：US06730201B1
公开(公告)日：2004-05-04
申请号：US09670902
申请日：2000-09-28
申请人： Kimberly Kuhlman , Martin G. Buehler
发明人： Kimberly Kuhlman , Martin G. Buehler
IPC分类号： G01N27333
CPC分类号： G01N27/27 , G01N27/3335
摘要： An ion selective electrode (ISE) array is described, as well as methods for producing the same. The array can contain multiple ISE which are individually electronically addressed. The addressing allows simplified preparation of the array. The array can be used for water quality monitoring, for example.
摘要翻译：描述了离子选择电极（ISE）阵列，以及其制备方法。阵列可以包含多个独立电子寻址的ISE。寻址允许简化阵列的准备。例如，该阵列可用于水质监测。

8. 发明授权

US5925823A Alpha-particle gas-pressure sensor 失效
标题翻译： α粒子气体压力传感器
公开(公告)号：US5925823A
公开(公告)日：1999-07-20
申请号：US897233
申请日：1997-05-30
申请人： Martin G. Buehler , L. Douglas Bell , Michael H. Hecht
发明人： Martin G. Buehler , L. Douglas Bell , Michael H. Hecht
IPC分类号： G01L21/32 , G01T1/18 , G01L7/00
CPC分类号： G01L21/32 , G01T1/18
摘要： Gas pressure in a chamber is determined by injecting alpha particles. The alpha particles ionize the gas. By determining a number of gas ions which are ionized, the pressure of the gas in the chamber can be determined.
摘要翻译：通过注入α粒子确定腔室中的气体压力。 α粒子将气体离子化。通过确定离子化的多个气体离子，可以确定腔室中气体的压力。

9. 发明授权

US5048023A Asymmetric soft-error resistant memory 失效
标题翻译：不对称软错误记忆
公开(公告)号：US5048023A
公开(公告)日：1991-09-10
申请号：US311024
申请日：1989-02-16
申请人： Martin G. Buehler , Marvin Perlman
发明人： Martin G. Buehler , Marvin Perlman
IPC分类号： G06F11/00 , G06F11/10 , G11C5/00 , H01L27/11
CPC分类号： G06F11/1008 , G06F11/1076 , G11C5/005 , H01L27/11 , G06F11/1036
摘要： A memory system is provided, of the type which includes an error-correcting circuit that detects and corrects errors, which more efficiently utilizes the capacity of a memory formed of groups of binary cells whose states can be inadvertently switched by ionizing radiation. Each memory cell has an asymmetric geometry, so that ionizing radiation causes a significantly greater probability of errors in one state than in the opposite state (e.g., an erroneous switch from "1" to "0" is far more likely than a switch from "0" to "1"). An asymmetric error-correcting coding circuit can be used with the asymmetric memory cells, which requires fewer bits than an efficient symmetric error-correcting code.
摘要翻译：提供了一种存储系统，其类型包括检错纠错误差，其更有效地利用由状态可能被电离辐射无意中切换的二进制单元组形成的存储器的容量。每个存储单元具有非对称几何形状，使得电离辐射在一个状态中导致比在相反状态下更大的误差概率（例如，从“1”到“0”的错误转换比从“ 0“到”1“）。非对称误差校正编码电路可以与非对称存储器单元一起使用，这需要比有效的对称误差校正码少的位。

10. 发明授权

US4918377A Integrated circuit reliability testing 失效
标题翻译：集成电路可靠性测试
公开(公告)号：US4918377A
公开(公告)日：1990-04-17
申请号：US279676
申请日：1988-12-05
申请人： Martin G. Buehler , Hoshyar R. Sayah
发明人： Martin G. Buehler , Hoshyar R. Sayah
IPC分类号： G01R31/30
CPC分类号： G01R31/30
摘要： A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the "measured length" of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit.
摘要翻译：描述了一种用于确定沉积在集成电路器件的不平坦表面上的微细导体的可靠性的技术。含有集成电路芯片的晶片形成有具有不同高度区域的测试区域。当导体形成在晶片的芯片区域上时，细长的蛇形测试导体沉积在测试区域上，使得测试导体在不同高度的区域之间延伸多个步骤。此外，第一测试导体在第一高度的均匀区域上沉积在测试区域中，并且第二测试导体在第二高度的均匀区域上沉积在测试区域中。通过使用在蛇形导体的端部之间测量的电阻，并将其与蛇形导体的设计长度进行比较，得出蛇形导体的“测量长度”来指示不同高度的区域之间的台阶处的高电阻的出现。测量长度超过集成电路丢弃的设计长度的百分比取决于集成电路所需的可靠性。

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