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1. 发明授权

US06646580B2 Digital/analog converter with programmable gain 有权
标题翻译：带可编程增益的数字/模拟转换器
公开(公告)号：US06646580B2
公开(公告)日：2003-11-11
申请号：US10012009
申请日：2001-10-29
申请人： Martin Clara , Hubert Weinberger , Christian Fleischhacker , Andreas Wiesbauer
发明人： Martin Clara , Hubert Weinberger , Christian Fleischhacker , Andreas Wiesbauer
IPC分类号： H03M100
CPC分类号： H03M1/66
摘要： Digital/analog converter with programmable gain for converting a digital input signal (Dn) into an analog output signal, the digital/analog converter (1) having: a signal input (2) for applying the digital input signal (Dn) a reference current source (7) for generating a reference current (Iref&phgr;), the current intensity of the reference current output by the reference current source (7) being adjustable via a setting terminal (4) of the digital/analog converter (1) current mirror circuits which mirror the generated reference current (Iref) with an associated current mirror ratio to form mirror currents a controllable switching device (57), which switches through the mirror currents output by the current mirror circuits, in a manner dependent on the digital input signal (Dn) present at the signal input (2), to a summation current node (62) for generating a summation current (Isum) and a current/voltage converter (17) for converting the generated summation current (Isum) into a corresponding voltage (UA), which is output as an analog output signal via an analog signal output (3) of the digital/analog converter (1).
摘要翻译：具有用于将数字输入信号（Dn）转换为模拟输出信号的可编程增益的数字/模拟转换器，所述数/模转换器（1）具有：用于施加数字输入信号（Dn）的信号输入（2）用于产生参考电流（Irefphi）的源（7），由参考电流源（7）输出的参考电流的电流强度可经由数字/模拟转换器（1）的设置端子（4）调节，电流镜像电路其以相关联的电流镜像比来反映所产生的参考电流（Iref），以形成镜像电流。可控开关器件（57）以取决于数字输入信号（Dn）的方式切换由电流镜电路输出的镜电流）存在于用于产生求和电流（Isum）的和电流节点（62）和用于将产生的求和电流（Isum）转换成相应的电流/电压转换器（17）的电流/电压转换器（17）电压（UA），通过数/模转换器（1）的模拟信号输出（3）作为模拟输出信号输出。

2. 发明授权

US06879273B2 Oversampling in analog/digital and digital/analog converters 有权
标题翻译：模拟/数字和数字/模拟转换器中的过采样
公开(公告)号：US06879273B2
公开(公告)日：2005-04-12
申请号：US10669280
申请日：2003-09-23
申请人： Andreas Wiesbauer , Martin Clara , Thomas Pötscher , Hubert Weinberger , Jörg Hauptmann , Thomas Magesacher
发明人： Andreas Wiesbauer , Martin Clara , Thomas Pötscher , Hubert Weinberger , Jörg Hauptmann , Thomas Magesacher
IPC分类号： H03M1/00 , H03M1/20 , H03M1/66 , H03M3/00 , H04B14/04 , H04B14/06
CPC分类号： H03M1/66 , H03M1/201 , H03M3/33 , H03M3/458 , H03M3/50
摘要： The invention creates a method and a device for digitally transmitting analog signals, in which oversampling is performed in analog/digital and digital/analog converters. In this arrangement, a digital/analog conversion is performed which, in particular, is suitable for VDSL systems. A transmitted digital transmission signal (110) is supplied to a mixing unit (201) and in the mixing unit (201), a receive noise signal (211) applied to a receive noise source terminal (209) is superimposed on the digital transmission signal (110). An interpolation filter unit (203), in combination with a subsequent noise shaping device (205), provides an increase in the frequency bandwidth, resulting in suitable oversampling.
摘要翻译：本发明创建了一种用于数字传输模拟信号的方法和装置，其中在模拟/数字和数字/模拟转换器中执行过采样。在这种布置中，执行数字/模拟转换，其特别适用于VDSL系统。传输的数字传输信号（110）被提供给混合单元（201）并且在混合单元（201）中，施加到接收噪声源终端（209）的接收噪声信号（211）被叠加在数字传输信号（110）。与随后的噪声整形装置（205）组合的内插滤波器单元（203）提供频率带宽的增加，从而导致合适的过采样。

3. 发明授权

US06496128B2 Sigma-delta analog-to-digital converter array 有权
公开(公告)号：US06496128B2
公开(公告)日：2002-12-17
申请号：US10001022
申请日：2001-11-02
申请人： Andreas Wiesbauer , Hubert Weinberger , Martin Clara , Jörg Hauptmann
发明人： Andreas Wiesbauer , Hubert Weinberger , Martin Clara , Jörg Hauptmann
IPC分类号： H03M300
CPC分类号： H03M3/416
摘要： A sigma-delta analog-to-digital converter array including two cascaded sigma-delta modulators, the two sigma-delta modulators being multi-bit sigma-delta modulators. The sigma-delta analog-to-digital converter array is preferably a third order device and supplies a digital output signal corresponding to a sigma-delta converter with 7-bit quantization. To this end, a second order sigma-delta modulator with 3-bit quantization and a first order sigma-delta modulator with 5-bit quantization may be used.

4. 发明授权

US07642877B2 Self-oscillating modulator and method for adjusting a self-oscillating modulator 有权
标题翻译：自振荡调制器和调节自振荡调制器的方法
公开(公告)号：US07642877B2
公开(公告)日：2010-01-05
申请号：US11517640
申请日：2006-09-08
申请人： Martin Clara , Thomas Poetscher , Sergio Walter , Andreas Wiesbauer
发明人： Martin Clara , Thomas Poetscher , Sergio Walter , Andreas Wiesbauer
IPC分类号： H03K7/08
CPC分类号： H03K7/08 , H03F3/2171
摘要： A self-oscillating pulse-width modulator comprises an input, an output and a control loop. The control loop comprises a forward branch and a feedback loop. The forward branch is connected between the input and the output and comprises a comparator and a delay element. The feedback loop loops back to the input a feedback signal which depends on an output signal present at the output. The phase shift of the open control loop is 180° at the frequency of an oscillation to be generated by the modulator. At least a part of the phase shift is realized in the forward branch by means of the at least one delay element.
摘要翻译：自振荡脉冲宽度调制器包括输入，输出和控制环路。控制回路包括正向分支和反馈回路。正向分支连接在输入和输出之间，包括比较器和延迟元件。反馈环路回馈到输入端，反馈信号取决于输出端存在的输出信号。在由调制器产生的振荡频率下，开路控制环路的相移为180°。通过至少一个延迟元件在正向分支中实现至少一部分相移。

5. 发明授权

US07486214B1 Tuning methods for loop-filters of continuous-time sigma-delta modulators 有权
标题翻译：连续时间Σ-Δ调制器的环路滤波器的调谐方法
公开(公告)号：US07486214B1
公开(公告)日：2009-02-03
申请号：US11850000
申请日：2007-09-04
申请人： Antonio Di Giandomenico , David San Segundo Bello , Andreas Wiesbauer , Fabio Ballarin , Martin Clara
发明人： Antonio Di Giandomenico , David San Segundo Bello , Andreas Wiesbauer , Fabio Ballarin , Martin Clara
IPC分类号： H03M3/00
CPC分类号： H03M3/386 , H03M3/458
摘要： Techniques for tuning filters of modulation circuits are described herein.
摘要翻译：本文描述了用于调谐电路的调谐滤波器的技术。

6. 发明授权

US08027279B2 Echo cancellation 有权
标题翻译：回声取消
公开(公告)号：US08027279B2
公开(公告)日：2011-09-27
申请号：US11856071
申请日：2007-09-17
申请人： Martin Clara , Christian Fleischhacker , Wolfgang Klatzer , Tina Thelesklav
发明人： Martin Clara , Christian Fleischhacker , Wolfgang Klatzer , Tina Thelesklav
IPC分类号： H04B3/20 , H04M1/58
CPC分类号： H04B3/23
摘要： Embodiments related to echo compensation have been described and depicted.
摘要翻译：已经描述和描绘了与回波补偿有关的实施例。

7. 发明授权

US07928800B2 Programmable compensation network for operational amplifiers 有权
标题翻译：运算放大器的可编程补偿网络
公开(公告)号：US07928800B2
公开(公告)日：2011-04-19
申请号：US12327739
申请日：2008-12-03
申请人： Fabio Ballarin , Alfonso D'Andretta , Martin Clara , Antonio Di Giandomenico , Dario Giotta , Andreas Wiesbauer
发明人： Fabio Ballarin , Alfonso D'Andretta , Martin Clara , Antonio Di Giandomenico , Dario Giotta , Andreas Wiesbauer
IPC分类号： H03F1/36
CPC分类号： H03F3/45475 , H03F3/45183 , H03F2203/45528
摘要： Systems and methods for implementing a programmable network for a multimode conditionally stable operational amplifier are disclosed.
摘要翻译：公开了用于实现用于多模有条件稳定的运算放大器的可编程网络的系统和方法。

8. 发明授权

US07796072B2 Multiple mode sigma-delta modulator 有权
标题翻译：多模式Σ-Δ调制器
公开(公告)号：US07796072B2
公开(公告)日：2010-09-14
申请号：US12255038
申请日：2008-10-21
申请人： Antonio Di Giandomenico , David San Segundo Bello , Andreas Wiesbauer , Fabio Ballarin , Martin Clara
发明人： Antonio Di Giandomenico , David San Segundo Bello , Andreas Wiesbauer , Fabio Ballarin , Martin Clara
IPC分类号： H03M3/00
CPC分类号： H03M3/386 , H03M3/458
摘要： Modulation circuits for operating in at least a first and second mode are described herein.
摘要翻译：至少在第一和第二模式下操作的调制电路在此描述。

9. 发明授权

US07688236B2 Integrated circuit comprising a plurality of digital-to-analog converters, sigma-delta modulator circuit, and method of calibrating a plurality of multibit digital-to-analog converters 有权
标题翻译：包括多个数模转换器，Σ-Δ调制器电路以及校准多个数模转换器的方法的集成电路
公开(公告)号：US07688236B2
公开(公告)日：2010-03-30
申请号：US11865539
申请日：2007-10-01
申请人： Antonio Di Giandomenico , Martin Clara , David San Segundo Bello , Wolfgang Klatzer , Luca Gori , Andreas Wiesbauer
发明人： Antonio Di Giandomenico , Martin Clara , David San Segundo Bello , Wolfgang Klatzer , Luca Gori , Andreas Wiesbauer
IPC分类号： H03M1/10
CPC分类号： H03M1/1033 , H03M1/742 , H03M3/386 , H03M3/424 , H03M3/454
摘要： In an integrated circuit including a first multibit digital-to-analog converter and a second multibit digital-to-analog converter, a calibration circuit is provided which is shared between the first and second digital-to-analog converters.
摘要翻译：在包括第一多位数模转换器和第二多位数模转换器的集成电路中，提供了在第一和第二数模转换器之间共享的校准电路。

10. 发明申请

US20080297385A1 Sigma-Delta Analog-Digital Converter For An Xdsl Multistandard Input Stage 失效
标题翻译：用于Xdsl多标准输入级的Sigma-Delta模拟数字转换器
公开(公告)号：US20080297385A1
公开(公告)日：2008-12-04
申请号：US11661627
申请日：2004-09-02
申请人： Martin Clara , Antonio Di Giandomenico , Joerg Hauptmann , Andreas Wiesbauer
发明人： Martin Clara , Antonio Di Giandomenico , Joerg Hauptmann , Andreas Wiesbauer
IPC分类号： H03M3/04
CPC分类号： H03M3/394 , H03M3/406 , H03M3/424 , H03M3/452
摘要： The invention relates to a sigma-delta analogue/digital converter for an xDSL multi-standard input stage for converting an xDSL signal into a digital output signal, where the sigma-delta analogue/digital converter (1) has: an analogue loop filter (6) which filters an analogue difference signal between the xDSL signal to be converted and a feedback signal in order to produce a filter output signal; a quantizer which quantizes the filter output signal from the analogue loop filter (6) in order to produce the digital output signal; a first digital/analogue converter (16) which converts the digital output signal into the analogue feedback signal; where the analogue loop filter (6) has at least two resonator filter stages (6a, 6b) which respectively comprise a first integrator (6a-1; 6b-1) and a second integrator (6a-2; 6b-2) connected in series therewith, where the second integrator (6a-2; 6b-2) can be connected to the first integrator (6a-1, 6b-1) by means of a controllable feedback switch (6a-3, 6b-3) in order to close a local feedback loop, where the integrator outputs can respectively be connected by means of a controllable switch (25) to a signal input of an adder (27) which adds the output signals from the integrators in order to produce the filter output signal.
摘要翻译：本发明涉及一种用于xDSL多标准输入级的Σ-Δ模拟/数字转换器，用于将xDSL信号转换成数字输出信号，其中Σ-Δ模拟/数字转换器（1）具有：模拟环路滤波器 6），其对要转换的xDSL信号和反馈信号之间的模拟差分信号进行滤波，以产生滤波器输出信号; 量化器，其量化来自模拟环路滤波器（6）的滤波器输出信号，以产生数字输出信号; 第一数字/模拟转换器（16），其将数字输出信号转换成模拟反馈信号; 其中模拟环路滤波器（6）具有至少两个分别包括第一积分器（6a-1; 6b-1）和第二积分器（6a-2; 6b-2）的谐振器滤波器级（6a，6b）其中第二积分器（6a-2; 6b-2）可以通过可控反馈开关（6a-3,6b-3）按顺序连接到第一积分器（6a-1,6b-1）以闭合局部反馈回路，其中积分器输出可以分别通过可控开关（25）连接到加法器（27）的信号输入端，加法器（27）的信号输入相加来自积分器的输出信号，以产生滤波器输出信号。

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