专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5913115A Method for producing a CMOS circuit 失效
标题翻译： CMOS电路的制造方法
公开(公告)号：US5913115A
公开(公告)日：1999-06-15
申请号：US67766
申请日：1998-04-29
申请人： Markus Biebl , Udo Schwalke , Herbert Schaefer , Dirk Schumann
发明人： Markus Biebl , Udo Schwalke , Herbert Schaefer , Dirk Schumann
IPC分类号： H01L27/092 , H01L21/20 , H01L21/8238 , H01L21/265
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L21/823814
摘要： In producing a CMOS circuit, an n-channel MOS transistor and a p-channel MOS transistor are formed in a semiconductor substrate. In situ p-doped, monocrystalline silicon structures are formed by epitaxial growth selectively with respect to insulating material and with respect to n-doped silicon, such silicon structures being suitable as a diffusion source for forming source/drain regions of the p-channel MOS transistor. The source/drain regions of the n-channel MOS transistor are produced beforehand by means of implantation or diffusion. Owing to the selectivity of the epitaxy that is used, it is not necessary to cover the n-doped source/drain regions of the n-channel MOS transistor during the production of the p-channel MOS transistor.
摘要翻译：在制造CMOS电路时，在半导体衬底中形成n沟道MOS晶体管和p沟道MOS晶体管。原位p掺杂的单晶硅结构通过相对于绝缘材料选择性地外延生长而形成，并且对于n掺杂的硅，这种硅结构适合作为用于形成p沟道MOS的源极/漏极区的扩散源晶体管。 n沟道MOS晶体管的源极/漏极区域通过注入或扩散预先产生。由于使用的外延的选择性，在制造p沟道MOS晶体管期间不需要覆盖n沟道MOS晶体管的n掺杂源极/漏极区域。

2. 外观设计

USD652988S1 Hand dryer 有权
公开(公告)号：USD652988S1
公开(公告)日：2012-01-24
申请号：US29373565
申请日：2011-04-27
申请人： Dirk Schumann
设计人： Dirk Schumann

3. 发明申请

US20060102815A1 Apparatus for setting the spacing of a free standing range from a floor 有权
标题翻译：用于从地板设定自由站立距离的间隔的装置
公开(公告)号：US20060102815A1
公开(公告)日：2006-05-18
申请号：US10988247
申请日：2004-11-12
申请人： Klaus Erdmann , George May , Dirk Schumann
发明人： Klaus Erdmann , George May , Dirk Schumann
IPC分类号： F16M11/24
CPC分类号： A47L15/4253 , D06F39/125 , F16M7/00
摘要： An apparatus for setting the spacing of a free standing range relative to a floor includes a base component for contacting the floor, a threaded element, and a winding follower. The winding follower extends into the helical recess of the threaded element such that the winding follower travels progressively further along the helical recess of the threaded element. A blocking member engages the winding follower during travel of the winding follower along the helical recess of the threaded element to resist a disengagement movement.
摘要翻译：用于设定相对于地板的自由站立范围的间隔的装置包括用于接触地板的基座部件，螺纹元件和绕组从动件。绕组从动件延伸到螺纹元件的螺旋凹槽中，使得绕组从动件沿螺纹元件的螺旋凹槽进一步进一步移动。在绕线从动件沿着螺纹元件的螺旋凹槽行进期间，阻挡构件接合绕组从动件以抵抗分离运动。

4. 发明授权

US06987295B2 Trench capacitor and method for fabricating the trench capacitor 失效
标题翻译：沟槽电容器和制造沟槽电容器的方法
公开(公告)号：US06987295B2
公开(公告)日：2006-01-17
申请号：US10650817
申请日：2003-08-28
申请人： Bernhard Sell , Annette Sänger , Dirk Schumann
发明人： Bernhard Sell , Annette Sänger , Dirk Schumann
IPC分类号： H01L27/108
CPC分类号： H01L27/10861 , H01L27/1203
摘要： A trench capacitor for use in a DRAM memory cell contains a lower capacitor electrode, a storage dielectric, and an upper capacitor electrode, which are at least partially disposed in a trench. The lower capacitor electrode adjoins, in a lower trench region, a wall of the trench, while in the upper trench region there is a spacer layer that adjoins a wall of the trench and is made from an insulating material. The upper electrode contains at least three layers, a first layer disposed in the trench on the storage dielectric and containing doped polysilicon, a second layer disposed on the first layer and containing metal-silicide, and a third layer disposed on the second layer and containing doped polysilicon. The layers of the upper electrode in each case extending along the walls and the base of the trench up to at least the upper edge of the spacer layer.
摘要翻译：用于DRAM存储单元的沟槽电容器包括至少部分地设置在沟槽中的下电容器电极，存储电介质和上电容器电极。下部电容器电极在下部沟槽区域中邻接沟槽的壁，而在上部沟槽区域中存在间隔层，该间隔层邻接沟槽的壁并由绝缘材料制成。上电极包含至少三层，第一层设置在存储电介质上的沟槽中并含有掺杂多晶硅，第二层设置在第一层上并含有金属硅化物，第三层设置在第二层上并含有掺杂多晶硅。每个壳体中的上电极的层沿着沟槽的壁和基底延伸到至少间隔层的上边缘。

5. 发明授权

US08834643B2 Method and composition for cleaning objects 有权
标题翻译：清洁物品的方法和组成
公开(公告)号：US08834643B2
公开(公告)日：2014-09-16
申请号：US13259536
申请日：2010-03-22
申请人： Dirk Schumann , Rainer Surkow
发明人： Dirk Schumann , Rainer Surkow
IPC分类号： B08B3/04 , C11D3/18 , C11D3/20 , C11D17/00 , C11D3/00 , C11D3/32 , C11D1/825 , C11D1/83
CPC分类号： C11D17/0021 , C11D1/825 , C11D1/83 , C11D3/0052 , C11D3/18 , C11D3/20 , C11D3/201 , C11D3/2041 , C11D3/2072 , C11D3/2093 , C11D3/32
摘要： A method for cleaning objects made of organic or inorganic materials, wherein the relevant material is brought into contact with a composition in the form of a fluid nanophase system, comprising a) at least one water-insoluble substance having a water solubility of less than 4 grams per liter, b) at least one amphiphilic substance (NP-MCA) which has no surfactant structure, is not structure-forming on its own, the solubility of which in water or oil ranges between 4 g and 1000 g per liter and which does not preferably accumulate at the oil-water interface, c) at least one anionic, cationic, amphoteric and/or non-ionic surfactant, d) at least one polar protic solvent, in particular having hydroxy functionality, e) if necessary one or more auxiliary substance.
摘要翻译：一种用于清洁由有机或无机材料制成的物体的方法，其中所述相关材料与流体纳米相系统形式的组合物接触，所述组合物包含：a）至少一种具有小于4的水溶性的水不溶性物质克/升，b）至少一种不具有表面活性剂结构的两亲物质（NP-MCA）本身不是结构形成的，其在水或油中的溶解度范围为4g至1000g / l，其中不优选在油 - 水界面处积聚，c）至少一种阴离子，阳离子，两性和/或非离子表面活性剂，d）至少一种极性质子溶剂，特别是具有羟基官能团，e）更多辅助物质。

6. 发明授权

US06835612B2 Method for fabricating a MOSFET having a very small channel length 失效
标题翻译：用于制造具有非常小的沟道长度的MOSFET的方法
公开(公告)号：US06835612B2
公开(公告)日：2004-12-28
申请号：US10673705
申请日：2003-09-26
申请人： Annalisa Cappellani , Ludwig Dittmar , Dirk Schumann
发明人： Annalisa Cappellani , Ludwig Dittmar , Dirk Schumann
IPC分类号： H01L21336
CPC分类号： H01L21/28114 , H01L21/2652 , H01L21/28052 , H01L21/28061 , H01L21/28123 , H01L21/32137 , H01L29/66575
摘要： A gate layer stack formed with at least two layers is firstly patterned anisotropically and then thelower layer is etched. An isotropic, preferably selective etching step effects a lateral undercutting, i.e. removal of the lower layer as far as the predetermined channel length to form a dimensionally accurate T-gate transistor with a very short channel length.
摘要翻译：形成有至少两层的栅极层叠层首先被各向异性地图案化，然后蚀刻低温层。各向同性，优选选择性蚀刻步骤实现横向底切，即将下层除去至预定沟道长度，以形成具有非常短的沟道长度的尺寸精确的T栅极晶体管。

7. 发明申请

US20110203571A1 CONTROL ELEMENT FOR A HOUSEHOLD APPLIANCE 审中-公开
标题翻译：家用电器的控制元件
公开(公告)号：US20110203571A1
公开(公告)日：2011-08-25
申请号：US13124677
申请日：2009-10-21
申请人： Nikolaus Schnetzer , Dirk Schumann
发明人： Nikolaus Schnetzer , Dirk Schumann
IPC分类号： F24C3/12 , B21D39/00 , C25D5/56
CPC分类号： C25D7/00 , C25D5/12 , C25D5/56 , G05G1/10 , Y10T428/12535
摘要： A control element for a household appliance is provided. The control element has a base member made of plastic. The base member has a nickel coating, and a noble metal coating is applied to the nickel coating.
摘要翻译：提供家用电器的控制元件。控制元件具有由塑料制成的基座部件。基底部件具有镍涂层，并且向镍涂层施加贵金属涂层。

8. 发明授权

US07866614B2 Apparatus for setting the spacing of a free standing range from a floor 有权
公开(公告)号：US07866614B2
公开(公告)日：2011-01-11
申请号：US10988247
申请日：2004-11-12
申请人： Klaus Erdmann , George May , Dirk Schumann
发明人： Klaus Erdmann , George May , Dirk Schumann
IPC分类号： F16M11/24
CPC分类号： A47L15/4253 , D06F39/125 , F16M7/00
摘要： An apparatus for setting the spacing of a free standing range relative to a floor includes a base component for contacting the floor, a threaded element, and a winding follower. The winding follower extends into the helical recess of the threaded element such that the winding follower travels progressively further along the helical recess of the threaded element. A blocking member engages the winding follower during travel of the winding follower along the helical recess of the threaded element to resist a disengagement movement.

9. 发明授权

US07074317B2 Method for fabricating trench capacitors for large scale integrated semiconductor memories 失效
标题翻译：用于制造用于大规模集成半导体存储器的沟槽电容器的方法
公开(公告)号：US07074317B2
公开(公告)日：2006-07-11
申请号：US10436427
申请日：2003-05-12
申请人： Albert Birner , Dirk Schumann , Matthias Goldbach
发明人： Albert Birner , Dirk Schumann , Matthias Goldbach
IPC分类号： H05K3/07
CPC分类号： H01L21/3063 , C25F3/12 , H01L27/10861 , H01L28/40
摘要： An electrochemical method is provided for producing trenches for trench capacitors in p-doped silicon with a very high diameter/depth aspect ratio for large scale integrated semiconductor memories. Trenches (macropores) having a diameter of less than about 100 nm and a depth of more than 10 μm can be produced on p-doped silicon having a very low resistivity at a high etching rate.
摘要翻译：提供电化学方法用于在p掺杂硅中制造用于大规模集成半导体存储器的非常高的直径/深度纵横比的沟槽电容器的沟槽。可以以高蚀刻速率在具有非常低电阻率的p掺杂硅上产生直径小于约100nm且深度大于10um的沟槽（大孔）。

10. 发明申请

US20060073659A1 Method for fabricating a storage capacitor 审中-公开
标题翻译：存储电容器的制造方法
公开(公告)号：US20060073659A1
公开(公告)日：2006-04-06
申请号：US11285639
申请日：2005-11-22
申请人： Bernhard Sell , Annette Sanger , Dirk Schumann
发明人： Bernhard Sell , Annette Sanger , Dirk Schumann
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861 , H01L21/02164 , H01L21/0217 , H01L21/02271 , H01L21/28518 , H01L21/31604 , H01L27/10814 , H01L28/60
摘要： The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode. The lower, metallic capacitor electrode is formed in a self-aligned manner on a silicon base material in such a way that uncovered silicon regions are first produced at locations at which the lower capacitor electrode will be formed, and then metal silicide is selectively formed on the uncovered silicon regions.
摘要翻译：本发明涉及一种用于制造设计为沟槽或层叠电容器的存储电容器的新颖方法，特别用于DRAM存储单元。该方法包括形成下部金属电容器电极，存储电介质和上部电容器电极的步骤。下部金属电容器电极以自对准的方式形成在硅基材上，使得首先在将形成下电容器电极的位置处产生未覆盖的硅区域，然后选择性地形成金属硅化物未覆盖的硅区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式