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    • 2. 发明授权
    • Hybrid CCD imaging
    • 混合CCD成像
    • US5449908A
    • 1995-09-12
    • US175876
    • 1993-12-30
    • Mark V. WadsworthSebastian R. BorrelloRoland W. Gooch
    • Mark V. WadsworthSebastian R. BorrelloRoland W. Gooch
    • H01L27/148
    • H01L27/14881H01L27/14856
    • A hybrid semiconductor imaging structure comprising a high speed signal conditioning substrate (e.g. Si 12) and an imaging substrate (e.g. HgCdTe 10) mounted on the conditioning substrate using an adhesive layer (e.g. epoxy 31). Infrared-sensitive time delay and integration CCD columns (14) charge coupled to sense nodes (e.g. diodes 16) are disposed in the imaging substrate. High speed signal processing channels (e.g. capacitive transimpedance amplifier 18, correlated double sampling circuit 20 and multiplexing shift register 22) are disposed in the conditioning substrate. The sense nodes are connected to the signal processing channels with low capacitance hybrid leads (e.g A1 17).
    • 包括使用粘合剂层(例如环氧树脂31)安装在调理基板上的高速信号调理基板(例如Si 12)和成像基板(例如HgCdTe 10)的混合半导体成像结构。 耦合到感测节点(例如二极管16)的红外敏感时间延迟和积分CCD列(14)被布置在成像衬底中。 高速信号处理通道(例如,电容跨阻放大器18,相关双采样电路20和复用移位寄存器22)设置在调理基板中。 感测节点连接到具有低电容混合引线(例如A1 17)的信号处理通道。
    • 6. 发明授权
    • FET structure for use in narrow bandgap semiconductors
    • 用于窄带隙半导体的FET结构
    • US5274263A
    • 1993-12-28
    • US647373
    • 1991-01-28
    • Mark V. Wadsworth
    • Mark V. Wadsworth
    • H01L21/34H01L21/8254H01L27/148H01L29/22H01L29/78H01L21/265
    • H01L29/66969H01L21/8254H01L27/14875H01L29/22H01L29/78
    • A FET structure for use in narrow bandgap semiconductors comprising a narrow bandgap semiconductor substrate 24, an implanted source region 12 of a conductivity type opposite that of the substrate 24, an implanted drain region 12 of the same conductivity type as source region 12 and spaced from source region 12, a first diode guard ring 14 insulatively disposed on the substrate 24 and surrounding source region 12, a second diode guard ring 14 insulatively disposed on the substrate 24 and surrounding drain region 12, a gate region 16 insulatively disposed on the substrate 24 and surrounding the source and drain regions 12 and the first and second diode guard rings 14, an outer periphery transistor guard ring 18 insulatively disposed on the substrate 24 and surrounding the gate region 16 and a field plate region 20 insulatively disposed on the substrate 24 and surrounding the outer periphery transistor guard ring 18.Other devices, systems and methods are also disclosed.
    • 用于窄带隙半导体的FET结构,包括窄带隙半导体衬底24,与衬底24相反的导电类型的注入源区12,与源区12相同的导电类型的注入漏区12, 源极区域12,绝缘地设置在衬底24上并围绕源极区域12的第一二极管保护环14,绝缘地设置在衬底24和围绕漏极区域12上的第二二极管保护环14,绝缘地设置在衬底24上的栅极区域16 并围绕源极和漏极区域12以及第一和第二二极管保护环14,绝缘地设置在基板24上并围绕栅极区域16的外围晶体管保护环18以及绝缘地设置在基板24上的场板区域20,以及 围绕外周边晶体管保护环18.还公开了其他装置,系统和方法。
    • 8. 发明授权
    • Bolometer array spectrometer
    • 分光光度计阵列光谱仪
    • US5777329A
    • 1998-07-07
    • US683997
    • 1996-07-19
    • Glenn H. WestphalMark V. Wadsworth
    • Glenn H. WestphalMark V. Wadsworth
    • G01J3/26G01J5/20
    • G01J5/20G01J3/26
    • A spectrometer (2500) including a detector integrated circuit (2501) which includes a linear array (2503) of 128 adjoining 2 by 10 superpixel bolometers in a package base (2530) and under an infrared transparent lid (2510) with a graded interference filter (2511). Filter (2511) has a rectangular shape and is a passband filter with a center wavelength which varies linearly along the direction of the long sides which is also the long direction of the linear array (2503) of bolometers. The center wavelength varies by a factor of about 2 over the length of the linear array (2503).
    • 一种包括检测器集成电路(2501)的光谱仪(2500),其包括在封装基座(2530)中并且具有渐变干涉滤光器(2510)的红外透明盖(2510)下方的128个相邻的2×10个超像素辐射热计的线性阵列(2503) (2511)。 滤光器(2511)具有矩形形状,并且是具有中心波长的通带滤光器,该中心波长沿长边方向线性变化,长边方向也是测辐射热计线性阵列(2503)的长方向。 中心波长在线性阵列(2503)的长度上变化约2倍。
    • 9. 发明授权
    • Resistor string DAC with improved speed
    • 电阻串DAC,速度提高
    • US6130634A
    • 2000-10-10
    • US219173
    • 1998-12-22
    • Mark V. WadsworthKirk D. Peterson
    • Mark V. WadsworthKirk D. Peterson
    • H03M1/76H03M1/66H03M1/78
    • H03M1/765
    • The speed performance of a resistive DAC can be improved by tailoring the selection switch size to the node location. For the simple case of a DAC used in a SAR-based ADC, the MSB code, which is activated during each SAR search, is the speed-limiting bit. Increasing the size of the switch on the node corresponding to the MSB will reduce the on-resistance of the FET and, therefore, the total resistance to ground from the node. The on-resistance can be changed markedly without substantially changing the total capacitance at the output node, since the sum of the parasitic from the remaining switches will far exceed the additional capacitance created by increasing the MSB FET.
    • 可以通过将选择开关尺寸调整到节点位置来提高阻性DAC的速度性能。 对于在基于SAR的ADC中使用的DAC的简单情况,在每次SAR搜索期间激活的MSB代码是速度限制位。 增加对应于MSB的节点上的开关的尺寸将减小FET的导通电阻,并因此降低对节点的总接地阻抗。 导通电阻可以显着改变,而不会实质上改变输出节点处的总电容,因为来自剩余开关的寄生的总和将远远超过通过增加MSB FET而产生的附加电容。