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1. 发明授权

US07616685B2 Method for channel tracking in an LMS adaptive equalizer for 8VSB 失效
标题翻译：用于8VSB的LMS自适应均衡器中的信道跟踪方法
公开(公告)号：US07616685B2
公开(公告)日：2009-11-10
申请号：US11776233
申请日：2007-07-11
申请人： Mark Fimoff , Jin Kim , Gregory J. Tomezak
发明人： Mark Fimoff , Jin Kim , Gregory J. Tomezak
IPC分类号： H03H7/30
CPC分类号： H04L25/03019 , H04L2025/03617 , H04L2025/03687
摘要： A method and system for channel tracking in an adaptive equalizer for a digital data receiver. The method includes determining a first set of tap weights and a second set of tap weights of the equalizer, and determining a difference between the first and second sets of tap weights. The method also includes determining an error estimate based on symbols received at the receiver, comparing the error estimate with a divergence threshold, and determining a step size factor based on the difference and the comparison.
摘要翻译：一种用于数字数据接收机的自适应均衡器中的信道跟踪的方法和系统。该方法包括确定均衡器的抽头权重的第一集合和抽头权重的第二集合，以及确定第一和第二抽头权重集之间的差异。该方法还包括基于在接收机处接收的符号来确定误差估计，将误差估计与发散阈值进行比较，以及基于差异和比较来确定步长因子。

2. 发明授权

US08385397B2 Method for determining the step size for an LMS adaptive equalizer for 8VSB 失效
标题翻译：用于确定8VSB的LMS自适应均衡器的步长的方法
公开(公告)号：US08385397B2
公开(公告)日：2013-02-26
申请号：US11687909
申请日：2007-03-19
申请人： Mark Fimoff , Jin Kim , Gregory J. Tomezak
发明人： Mark Fimoff , Jin Kim , Gregory J. Tomezak
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L27/06 , H04L25/03019 , H04L25/03203 , H04L2025/03382 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03636 , H04L2025/03687 , H04L2025/037 , H04L2025/03732 , H04L2025/03783 , H04N5/4401 , H04N21/4382
摘要： A method and system for determining a step size of an adaptive equalizer for a digital data receiver. The data received by the receiver includes coded symbols and uncoded symbols. The method includes determining a first error estimate based on decoded symbols corresponding to the coded symbols, determining a second error estimate based on the uncoded symbols, adaptively selecting the first error estimate or the second error estimate based on a convergence criterion, and determining a step size based on the selected error estimate.
摘要翻译：一种用于确定数字数据接收机的自适应均衡器的步长的方法和系统。由接收机接收的数据包括编码符号和未编码符号。该方法包括基于对应于编码符号的解码符号确定第一误差估计，基于未编码符号确定第二误差估计，基于收敛标准自适应地选择第一误差估计或第二误差估计，以及确定步骤基于所选误差估计的大小。

3. 发明申请

US20080175309A1 METHOD FOR CHANNEL TRACKING IN AN LMS ADAPTIVE EQUALIZER FOR 8VSB 失效
标题翻译：用于8VSB的LMS自适应均衡器中的信道跟踪方法
公开(公告)号：US20080175309A1
公开(公告)日：2008-07-24
申请号：US11776233
申请日：2007-07-11
申请人： Mark Fimoff , Jin Kim , Gregory J. Tomezak
发明人： Mark Fimoff , Jin Kim , Gregory J. Tomezak
IPC分类号： H04L25/03
CPC分类号： H04L25/03019 , H04L2025/03617 , H04L2025/03687
摘要： A method and system for channel tracking in an adaptive equalizer for a digital data receiver. The method includes determining a first set of tap weights and a second set of tap weights of the equalizer, and determining a difference between the first and second sets of tap weights. The method also includes determining an error estimate based on symbols received at the receiver, comparing the error estimate with a divergence threshold, and determining a step size factor based on the difference and the comparison.
摘要翻译：一种用于数字数据接收机的自适应均衡器中的信道跟踪的方法和系统。该方法包括确定均衡器的抽头权重的第一集合和抽头权重的第二集合，以及确定第一和第二抽头权重集之间的差异。该方法还包括基于在接收机处接收的符号来确定误差估计，将误差估计与发散阈值进行比较，以及基于差异和比较来确定步长因子。

4. 发明申请

US20080175308A1 METHOD FOR DETERMINING THE STEP SIZE FOR AN LMS ADAPTIVE EQUALIZER FOR 8VSB 失效
标题翻译：用于确定用于8VSB的LMS自适应均衡器的步长尺寸的方法
公开(公告)号：US20080175308A1
公开(公告)日：2008-07-24
申请号：US11687909
申请日：2007-03-19
申请人： Mark Fimoff , Jin Kim , Gregory J. Tomezak
发明人： Mark Fimoff , Jin Kim , Gregory J. Tomezak
IPC分类号： H03H7/40
CPC分类号： H04L27/06 , H04L25/03019 , H04L25/03203 , H04L2025/03382 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03636 , H04L2025/03687 , H04L2025/037 , H04L2025/03732 , H04L2025/03783 , H04N5/4401 , H04N21/4382
摘要： A method and system for determining a step size of an adaptive equalizer for a digital data receiver. The data received by the receiver includes coded symbols and uncoded symbols. The method includes determining a first error estimate based on decoded symbols corresponding to the coded symbols, determining a second error estimate based on the uncoded symbols, adaptively selecting the first error estimate or the second error estimate based on a convergence criterion, and determining a step size based on the selected error estimate.
摘要翻译：一种用于确定数字数据接收机的自适应均衡器的步长的方法和系统。由接收机接收的数据包括编码符号和未编码符号。该方法包括基于对应于编码符号的解码符号确定第一误差估计，基于未编码符号确定第二误差估计，基于收敛标准自适应地选择第一误差估计或第二误差估计，以及确定步骤基于所选误差估计的大小。

5. 发明申请

US20050254570A1 Channel impulse response estimating decision feedback equalizer 有权
标题翻译：信道脉冲响应估计判决反馈均衡器
公开(公告)号：US20050254570A1
公开(公告)日：2005-11-17
申请号：US10911282
申请日：2004-08-04
申请人： Bruno Amizic , Mark Fimoff , Jin Kim , Sreenivasa Nerayanuru
发明人： Bruno Amizic , Mark Fimoff , Jin Kim , Sreenivasa Nerayanuru
IPC分类号： H04L1/00 , H04L25/03 , H04L5/12
CPC分类号： H04L25/03057 , H04L2025/03382 , H04L2025/0349
摘要： A decision feedback equalizer is operated by making first symbol decisions from an output of the decision feedback equalizer such that the first symbol decisions are characterized by a relatively long processing delay, by making second symbol decisions from the output of the decision feedback equalizer such that the second symbol decisions are characterized by a relatively short processing delay, and by determining tap weights for the decision feedback equalizer based on the first and second symbol decisions. The first symbol decisions may be derived from the output of a long traceback trellis decoder. The second symbol decisions may be derived either from the output of a short traceback trellis decoder or from shorter delay outputs of the long traceback trellis decoder.
摘要翻译：通过从所述判决反馈均衡器的输出进行第一符号判定来操作判定反馈均衡器，以便通过从所述判决反馈均衡器的输出进行第二符号判定，使得所述第一符号判定由相对长的处理延迟表征，使得第二符号决定的特征在于相对短的处理延迟，并且通过基于第一和第二符号决定确定用于判决反馈均衡器的抽头权重。第一符号决定可以从长跟踪网格解码器的输出中导出。第二符号决定可以从短跟踪网格解码器的输出或长跟踪网格解码器的较短延迟输出中导出。

6. 发明授权

US08320442B2 Channel impulse response estimating decision feedback equalizer 有权
标题翻译：信道脉冲响应估计判决反馈均衡器
公开(公告)号：US08320442B2
公开(公告)日：2012-11-27
申请号：US10911282
申请日：2004-08-04
申请人： Bruno Amizic , Mark Fimoff , Jin Kim , Sreenivasa M. Nerayanuru
发明人： Bruno Amizic , Mark Fimoff , Jin Kim , Sreenivasa M. Nerayanuru
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H04L2025/03382 , H04L2025/0349
摘要： A decision feedback equalizer is operated by making first symbol decisions from an output of the decision feedback equalizer such that the first symbol decisions are characterized by a relatively long processing delay, by making second symbol decisions from the output of the decision feedback equalizer such that the second symbol decisions are characterized by a relatively short processing delay, and by determining tap weights for the decision feedback equalizer based on the first and second symbol decisions. The first symbol decisions may be derived from the output of a long traceback trellis decoder. The second symbol decisions may be derived either from the output of a short traceback trellis decoder or from shorter delay outputs of the long traceback trellis decoder.
摘要翻译：通过从所述判决反馈均衡器的输出进行第一符号判定来操作判定反馈均衡器，以便通过从所述判决反馈均衡器的输出进行第二符号判定，使得所述第一符号判定由相对长的处理延迟表征，使得第二符号决定的特征在于相对短的处理延迟，并且通过基于第一和第二符号决定确定用于判决反馈均衡器的抽头权重。第一符号决定可以从长跟踪网格解码器的输出中导出。第二符号决定可以从短跟踪网格解码器的输出或长跟踪网格解码器的较短延迟输出中导出。

7. 发明授权

US08640001B2 Robust digital communication system 有权
标题翻译：坚固的数字通信系统
公开(公告)号：US08640001B2
公开(公告)日：2014-01-28
申请号：US11931357
申请日：2007-10-31
申请人： Wayne E. Bretl , Richard W. Citta , Mark Fimoff
发明人： Wayne E. Bretl , Richard W. Citta , Mark Fimoff
IPC分类号： H03M13/00 , H03M13/03
CPC分类号： H04L25/03312 , H03M13/253 , H03M13/256 , H03M13/2732 , H03M13/2936 , H03M13/2957 , H03M13/6331 , H04L1/0041 , H04L1/0047 , H04L1/0054 , H04L1/0057 , H04L1/006 , H04L1/0065 , H04L1/007 , H04L1/0071 , H04L25/03267 , H04L25/03318 , H04L25/063 , H04L25/497 , H04L27/02 , H04L27/066 , H04L2025/03382 , H04N5/04 , H04N5/4401 , H04N5/455 , H04N21/23614 , H04N21/2383 , H04N21/4348 , H04N21/4382
摘要： Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust VSB data and reordered ATSC data are time multiplexed for transmission to a receiver. The receiver discards the reordered ATSC data or the normally ordered robust VSB data depending upon receiver type or user selection. A robust VSB receiver is able to process the normally ordered robust VSB data upstream of an outer decoder without an interleave thereby avoiding the delay associated with an interleave.
摘要翻译：根据第一交错，正常排序的鲁棒VSB数据被重新排序以产生重排序的鲁棒VSB数据。根据第二交错重新排序的稳健VSB数据和ATSC数据被重新排序以产生正常排序的鲁棒VSB数据和重新排序的ATSC数据。通常排序稳健的VSB数据和重新排序的ATSC数据被时分复用以传输到接收机。接收机根据接收机类型或用户选择丢弃重新排序的ATSC数据或正常排序的鲁棒VSB数据。稳健的VSB接收机能够处理在外部解码器上游的正常排序的鲁棒VSB数据，而不会产生交错，从而避免与交织相关联的延迟。

8. 发明申请

US20090180535A1 ROBUST DIGITAL COMMUNICATION SYSTEM 有权
标题翻译：强大的数字通信系统
公开(公告)号：US20090180535A1
公开(公告)日：2009-07-16
申请号：US12371688
申请日：2009-02-16
申请人： Wayne E. Bretl , Richard W. Citta , Mark Fimoff
发明人： Wayne E. Bretl , Richard W. Citta , Mark Fimoff
IPC分类号： H04N11/02 , H04J3/00
CPC分类号： H04L25/03312 , H03M13/253 , H03M13/256 , H03M13/2732 , H03M13/2936 , H03M13/2957 , H03M13/6331 , H04L1/0041 , H04L1/0047 , H04L1/0054 , H04L1/0057 , H04L1/006 , H04L1/0065 , H04L1/007 , H04L1/0071 , H04L25/03267 , H04L25/03318 , H04L25/063 , H04L25/497 , H04L27/02 , H04L27/066 , H04L2025/03382 , H04N5/04 , H04N5/4401 , H04N5/455 , H04N21/23614 , H04N21/2383 , H04N21/4348 , H04N21/4382
摘要： Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust VSB data and reordered ATSC data are time multiplexed for transmission to a receiver. The receiver discards the reordered ATSC data or the normally ordered robust VSB data depending upon receiver type or user selection. A robust VSB receiver is able to process the normally ordered robust VSB data upstream of an outer decoder without an interleave thereby avoiding the delay associated with an interleave.
摘要翻译：根据第一交错，正常排序的鲁棒VSB数据被重新排序以产生重排序的鲁棒VSB数据。根据第二交错重新排序的稳健VSB数据和ATSC数据被重新排序以产生正常排序的鲁棒VSB数据和重新排序的ATSC数据。通常排序稳健的VSB数据和重新排序的ATSC数据被时分复用以传输到接收机。接收机根据接收机类型或用户选择丢弃重新排序的ATSC数据或正常排序的鲁棒VSB数据。稳健的VSB接收机能够处理在外部解码器上游的正常排序的鲁棒VSB数据，而不会产生交错，从而避免与交织相关联的延迟。

9. 发明授权

US07382828B2 Channel impulse response (CIR) estimating decision feedback equalizer with phase tracker 有权
标题翻译：信道脉冲响应（CIR）估计具有相位跟踪器的判决反馈均衡器
公开(公告)号：US07382828B2
公开(公告)日：2008-06-03
申请号：US11114573
申请日：2005-04-26
申请人： Bruno Amizic , Mark Fimoff , Sreenivasa M. Nerayanuru
发明人： Bruno Amizic , Mark Fimoff , Sreenivasa M. Nerayanuru
IPC分类号： H03H7/30
CPC分类号： H04L25/0212 , H04L25/03057 , H04L25/03203
摘要： An equalizer system includes an equalizer, first and second decoders, and a tap weight controller. The equalizer equalizes a received signal to provide an equalizer output. The first decoder is characterized by a first parallel output, and the first decoder decodes the equalizer output to provide first symbol decisions having a first accuracy. The second decoder is characterized by a second parallel output, the second decoder receives the first parallel output and decodes the equalizer output to provide second symbol decisions having a second accuracy, the first accuracy is greater than the second accuracy, and the second decoder applies the second parallel output to the equalizer. The tap weight controller determines tap weights based on the first symbol decisions and supplies the tap weights to the equalizer.
摘要翻译：均衡器系统包括均衡器，第一和第二解码器以及抽头加权控制器。均衡器对接收到的信号进行均衡以提供均衡器输出。第一解码器的特征在于第一并行输出，并且第一解码器解码均衡器输出以提供具有第一精度的第一符号决定。第二解码器的特征在于第二并行输出，第二解码器接收第一并行输出并解码均衡器输出以提供具有第二精度的第二符号决定，第一精度大于第二精度，第二解码器应用第二并行输出到均衡器。抽头重量控制器基于第一符号决定确定抽头权重，并将抽头权重提供给均衡器。

10. 发明授权

US07382826B2 Method and apparatus for the control of a decision feedback equalizer 有权
标题翻译：用于控制决策反馈均衡器的方法和装置
公开(公告)号：US07382826B2
公开(公告)日：2008-06-03
申请号：US10766742
申请日：2004-01-27
申请人： Mark Fimoff , Sreenivasa M. Nerayanuru
发明人： Mark Fimoff , Sreenivasa M. Nerayanuru
IPC分类号： H03H7/30 , H04L25/03 , H04B3/14
CPC分类号： H04L25/03057 , H04L25/03267 , H04L2025/03382 , H04L2025/0349 , H04L2025/03605 , H04L2025/03726 , H04N5/211 , H04N5/4401
摘要： Input data segments of received symbols are continuously stored in a decision feedback equalizer buffer at a symbol rate S. Output data sections of received symbols are supplied from the decision feedback equalizer buffer at an output rate of nS such that void times separate the output data sections, and n>1. The received symbols supplied by the decision feedback equalizer buffer are equalized in a decision feedback equalizer to provide equalized symbols; and the equalized symbols are decoded by a decoder to provide decoded symbols. Adjustments for the decision feedback equalizer are calculated during the void times such that the adjustments are calculated based on both the received symbols supplied by the decision feedback equalizer buffer and the decoded symbols. The adjustments are applied to the decision feedback equalizer.
摘要翻译：接收到的符号的输入数据段以符号率S连续地存储在判定反馈均衡器缓冲器中。接收符号的输出数据部分以nS的输出速率从判决反馈均衡器缓冲器提供，使得空闲时间将输出数据部分，n> 1。由判决反馈均衡器缓冲器提供的接收符号在判决反馈均衡器中被均衡以提供均衡的符号; 并且均衡符号由解码器解码以提供解码的符号。在空闲时间期间计算用于判决反馈均衡器的调整，使得基于由判决反馈均衡器缓冲器和解码符号提供的接收符号两者来计算调整。调整应用于判决反馈均衡器。

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