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1. 发明申请

US20060006522A1 Forming dual metal complementary metal oxide semiconductor integrated circuits 有权
公开(公告)号：US20060006522A1
公开(公告)日：2006-01-12
申请号：US10889535
申请日：2004-07-12
申请人： Mark Doczy , Mitchell Taylor , Justin Brask , Jack Kavalieros , Suman Datta , Matthew Metz , Robert Chau , Jack Hwang
发明人： Mark Doczy , Mitchell Taylor , Justin Brask , Jack Kavalieros , Suman Datta , Matthew Metz , Robert Chau , Jack Hwang
IPC分类号： H01L23/14
CPC分类号： H01L21/823842
摘要： Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The metal layer may have a workfunction most suitable for forming one type of transistor, but is used to form both the n and p-type transistors. The workfunction of the metal layer may be converted, for example, by ion implantation to make it more suitable for use in forming transistors of the opposite type.

2. 发明授权

US07439113B2 Forming dual metal complementary metal oxide semiconductor integrated circuits 有权
标题翻译：形成双金属互补金属氧化物半导体集成电路
公开(公告)号：US07439113B2
公开(公告)日：2008-10-21
申请号：US10889535
申请日：2004-07-12
申请人： Mark Doczy , Mitchell Taylor , Justin K. Brask , Jack Kavalieros , Suman Datta , Matthew V. Metz , Robert S. Chau , Jack Hwang
发明人： Mark Doczy , Mitchell Taylor , Justin K. Brask , Jack Kavalieros , Suman Datta , Matthew V. Metz , Robert S. Chau , Jack Hwang
IPC分类号： H01L29/78
CPC分类号： H01L21/823842
摘要： Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The metal layer may have a workfunction most suitable for forming one type of transistor, but is used to form both the n and p-type transistors. The workfunction of the metal layer may be converted, for example, by ion implantation to make it more suitable for use in forming transistors of the opposite type.
摘要翻译：互补金属氧化物半导体金属栅极晶体管可以通过在先前由图案化栅极结构居住的沟槽中沉积金属层来形成。在一个实施例中，图案化栅极结构可以由多晶硅形成。金属层可以具有最适于形成一种类型的晶体管的功函数，但是用于形成n型和p型晶体管。可以例如通过离子注入来转换金属层的功函数，使其更适用于形成相反类型的晶体管。

3. 发明申请

US20090020825A1 Forming dual metal complementary metal oxide semiconductor integrated circuits 审中-公开
标题翻译：形成双金属互补金属氧化物半导体集成电路
公开(公告)号：US20090020825A1
公开(公告)日：2009-01-22
申请号：US12283217
申请日：2008-09-10
申请人： Mark Doczy , Mitchell Taylor , Justin K. Brask , Jack Kavalieros , Suman Datta , Matthew V. Metz , Robert S. Chau , Jack Hwang
发明人： Mark Doczy , Mitchell Taylor , Justin K. Brask , Jack Kavalieros , Suman Datta , Matthew V. Metz , Robert S. Chau , Jack Hwang
IPC分类号： H01L27/092
CPC分类号： H01L21/823842
摘要： Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The metal layer may have a workfunction most suitable for forming one type of transistor, but is used to form both the n and p-type transistors. The workfunction of the metal layer may be converted, for example, by ion implantation to make it more suitable for use in forming transistors of the opposite type.
摘要翻译：互补金属氧化物半导体金属栅极晶体管可以通过在先前由图案化栅极结构居住的沟槽中沉积金属层来形成。在一个实施例中，图案化栅极结构可以由多晶硅形成。金属层可以具有最适于形成一种类型的晶体管的功函数，但是用于形成n型和p型晶体管。可以例如通过离子注入来转换金属层的功函数，使其更适用于形成相反类型的晶体管。

4. 发明授权

US06808993B2 Ultra-thin gate dielectrics 有权
标题翻译：超薄栅电介质
公开(公告)号：US06808993B2
公开(公告)日：2004-10-26
申请号：US10339783
申请日：2003-01-08
申请人： Christine M. Finnie , Pauline N. Jacob , Nick Lindert , Keith M. Jackson , Kirk Althoff , Jack Hwang , Jack Kavalieros , James R. Mueller
发明人： Christine M. Finnie , Pauline N. Jacob , Nick Lindert , Keith M. Jackson , Kirk Althoff , Jack Hwang , Jack Kavalieros , James R. Mueller
IPC分类号： H01L21336
CPC分类号： H01L21/28202 , H01L21/28185 , H01L21/3144 , H01L21/3185 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： An in-situ ultra dilute ammonia nitridation process and apparatus of the following ultra-thin chemically tailored gate dielectrics: DCE/O2 (Trans 1,2-Dichloroethylene) based ultra-thin gate dielectric; Nitric Oxide (NO) based ultra-thin gate dielectric that has been re-oxidized via a DCE/O2 (Trans 1,2-Dichloroethylene) process; “dry-wet” DCE (Trans 1,2-Dichloroethylene)/O2-H2O/O2) based ultra-thin gate dielectric; and ultra dilute, less than 1E-7 moles NH3/mm2, nitridation of an ultra-thin gate dielectric. A vertical diffusion furnace (VDF) is provided to process the same. The ultra-thin chemically tailored gate dielectrics generated in a VDF with ultra-dilute NH3, below 1E-7 moles NH3/mm2, in-situ nitridation show a performance comparable or better to traditional ex-situ rapid thermal anneal (RTA) processing techniques for 90 nm CMOS technology. These methods replace and remove at least one process layer in the fabrication of CMOS devices using traditional ex-situ RTA processing, decreasing production costs, and improving fabrication cycle time, with equivalent or improved transistor performance.
摘要翻译：一种原位超稀氨氮工艺及以下超薄化学定制栅极电介质的设备：DCE / O2（Trans 1,2--Dichloroethylene））超薄栅极电介质; 已经通过DCE / O2（反式1,2-二氯乙烯）方法再氧化的一氧化氮（NO）基超薄栅极电介质; “干湿”DCE（反式1,2-二氯乙烯）/ O 2 -H 2 O / O 2）基超薄栅极电介质; 并且超稀释，小于1E-7摩尔NH 3 / mm 2，氮化超薄栅极电介质。提供垂直扩散炉（VDF）来处理它。在具有超稀释NH 3，低于1E-7摩尔NH 3 / mm 2的VDF中产生的超薄化学定制的栅极电介质在现场氮化显示出与传统的非原位快速热退火（RTA）相当或更好的性能）90nm CMOS技术的处理技术。这些方法在使用传统的异地RTA处理，降低生产成本和改进制造周期时间的CMOS器件制造中至少替代和去除至少一个工艺层，具有等效或改进的晶体管性能。

5. 发明申请

US20050191834A1 Creating shallow junction transistors 审中-公开
公开(公告)号：US20050191834A1
公开(公告)日：2005-09-01
申请号：US11122433
申请日：2005-05-05
申请人： Jack Hwang , Mitchell Taylor , Mark Liu , Nick Lindert
发明人： Jack Hwang , Mitchell Taylor , Mark Liu , Nick Lindert
IPC分类号： H01L21/223 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/6659 , H01L21/2236 , H01L21/28035 , H01L21/823814
摘要： A polysilicon structure may be defined on a semiconductor substrate using plasma doping to dope the sidewalls and upper surface of the polysilicon material as well as the source drain extensions. Shortly after plasma doping, the structure may be encapsulated within a suitable capping layer to prevent the removal of the thin surface doped regions during subsequent semiconductor processing.

6. 发明授权

US06638802B1 Forming strained source drain junction field effect transistors 有权
标题翻译：形成应变源极漏极结场效应晶体管
公开(公告)号：US06638802B1
公开(公告)日：2003-10-28
申请号：US10176336
申请日：2002-06-20
申请人： Jack Hwang , Craig Andyke , Mitchell Taylor
发明人： Jack Hwang , Craig Andyke , Mitchell Taylor
IPC分类号： H01L218234
CPC分类号： H01L29/66477 , H01L21/26506 , H01L21/26513 , H01L29/6653 , H01L29/7848
摘要： By providing a high dose germanium implant and then forming a P-type source/drain extension, a strained source/drain junction may be formed. The strained source/drain junction may be shallower and have lower resistivity in some embodiments.
摘要翻译：通过提供高剂量锗注入，然后形成P型源极/漏极延伸，可以形成应变源极/漏极结。在一些实施例中，应变源极/漏极结可以更浅并且具有较低的电阻率。

7. 发明申请

US20050158957A1 CREATING SHALLOW JUNCTION TRANSISTORS 失效
标题翻译：创建SHALLOW JUNCTION TRANSISTORS
公开(公告)号：US20050158957A1
公开(公告)日：2005-07-21
申请号：US10761550
申请日：2004-01-21
申请人： Jack Hwang , Mitchell Taylor , Mark Liu , Nick Lindert
发明人： Jack Hwang , Mitchell Taylor , Mark Liu , Nick Lindert
IPC分类号： H01L21/223 , H01L21/28 , H01L21/336 , H01L21/8238
CPC分类号： H01L29/6659 , H01L21/2236 , H01L21/28035 , H01L21/823814
摘要： A polysilicon structure may be defined on a semiconductor substrate using plasma doping to dope the sidewalls and upper surface of the polysilicon material as well as the source drain extensions. Shortly after plasma doping, the structure may be encapsulated within a suitable capping layer to prevent the removal of the thin surface doped regions during subsequent semiconductor processing.
摘要翻译：可以使用等离子体掺杂在半导体衬底上限定多晶硅结构以掺杂多晶硅材料的侧壁和上表面以及源极漏极延伸。在等离子体掺杂之后不久，该结构可以封装在合适的覆盖层内，以防止在随后的半导体处理期间去除薄表面掺杂区域。

8. 发明授权

US06911706B2 Forming strained source drain junction field effect transistors 有权
标题翻译：形成应变源极漏极结场效应晶体管
公开(公告)号：US06911706B2
公开(公告)日：2005-06-28
申请号：US10644417
申请日：2003-08-20
申请人： Jack Hwang , Craig Andyke , Mitchell Taylor
发明人： Jack Hwang , Craig Andyke , Mitchell Taylor
IPC分类号： H01L21/265 , H01L21/336 , H01L29/76
CPC分类号： H01L29/66477 , H01L21/26506 , H01L21/26513 , H01L29/6653 , H01L29/7848
摘要： By providing a high dose germanium implant and then forming a P-type source/drain extension, a strained source/drain junction may be formed. The strained source/drain junction may be shallower and have lower resistivity in some embodiments.
摘要翻译：通过提供高剂量锗注入，然后形成P型源极/漏极延伸，可以形成应变源极/漏极结。在一些实施例中，应变源极/漏极结可以较浅并且具有较低的电阻率。

9. 发明授权

US09054178B2 Self-aligned contacts 有权
标题翻译：自对准接触
公开(公告)号：US09054178B2
公开(公告)日：2015-06-09
申请号：US14174822
申请日：2014-02-06
申请人： Mark T. Bohr , Tahir Ghani , Nadia M. Rahhai-Orabi , Subhash M. Joshi , Joseph M. Steigerwald , Jason W. Klaus , Jack Hwang , Ryan Mackiewicz
发明人： Mark T. Bohr , Tahir Ghani , Nadia M. Rahhai-Orabi , Subhash M. Joshi , Joseph M. Steigerwald , Jason W. Klaus , Jack Hwang , Ryan Mackiewicz
IPC分类号： H01L29/417 , H01L29/78 , H01L29/06 , H01L21/768 , H01L29/66 , H01L29/51 , H01L29/49
CPC分类号： H01L21/76897 , H01L21/28123 , H01L21/28229 , H01L21/28255 , H01L21/283 , H01L21/28562 , H01L21/31105 , H01L21/76802 , H01L21/76831 , H01L21/76849 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/535 , H01L29/0847 , H01L29/16 , H01L29/42364 , H01L29/456 , H01L29/495 , H01L29/4966 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/66477 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/78 , H01L29/785 , H01L2029/7858 , H01L2924/0002 , H01L2924/00
摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.
摘要翻译：晶体管包括衬底，衬底上的一对间隔物，衬底上的栅介质层和一对间隔物之间，栅极电介质层上的栅电极层和一对衬垫之间的绝缘帽层栅极电极层和一对间隔物之间，以及与该对间隔物相邻的一对扩散区域。绝缘盖层形成了与栅极自对准的防蚀结构，并防止接触蚀刻暴露栅电极，从而防止栅极和接触之间的短路。绝缘体盖层能够进行自对准触点，允许对图案化限制更坚固的较宽触点的初始图案化。

10. 发明授权

US08426858B2 Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain 有权
公开(公告)号：US08426858B2
公开(公告)日：2013-04-23
申请号：US12956020
申请日：2010-11-30
申请人： Michael L. Hattendorf , Jack Hwang , Anand Murthy , Andrew N. Westmeyer
发明人： Michael L. Hattendorf , Jack Hwang , Anand Murthy , Andrew N. Westmeyer
IPC分类号： H01L29/04 , H01L31/036
CPC分类号： H01L29/66628 , H01L21/26506 , H01L29/7834 , H01L29/7842
摘要： Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.

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