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1. 发明授权

US06992674B2 Checkerboard buffer using two-dimensional buffer pages and using state addressing 失效
公开(公告)号：US06992674B2
公开(公告)日：2006-01-31
申请号：US10076942
申请日：2002-02-14
申请人： Mark Champion , Brian Dockter
发明人： Mark Champion , Brian Dockter
IPC分类号： G09G5/399
CPC分类号： H04N7/01 , G06T1/60 , G09G5/39 , G09G5/393 , G09G2340/0407 , G09G2352/00 , G09G2360/122 , G09G2360/123 , G09G2360/128 , G11C7/1042 , H04N5/14 , H04N5/46 , H04N5/7416 , H04N7/012 , H04N7/0132
摘要： Methods and apparatus for storing and retrieving data using two-dimensional arrays. In one implementation, a checkerboard buffer page system includes: a data source, providing data elements in a first order; a data destination, receiving data elements in a second order; memory devices each having memory pages, data elements stored in parallel to and retrieved in parallel from the memory devices; each buffer page having entries along a first dimension corresponding to the first order and entries along a second dimension corresponding to the second order, data elements stored in the first order and retrieved in the second order, at least one memory page stores data elements in multiple locations according to the first and second orders, at least two data elements consecutive in the first order stored in parallel, and where at least two data elements consecutive in the second order retrieved in parallel.

2. 发明授权

US06801204B2 Checkerboard buffer using memory blocks 有权
标题翻译：使用内存块的棋盘缓冲区
公开(公告)号：US06801204B2
公开(公告)日：2004-10-05
申请号：US09907854
申请日：2001-07-17
申请人： Mark Champion , Brian Dockter
发明人： Mark Champion , Brian Dockter
IPC分类号： G06F1328
CPC分类号： H04N7/01 , G06T1/60 , G09G3/001 , G09G5/39 , G09G5/393 , G09G5/399 , G09G2352/00 , G09G2360/122 , G09G2360/123 , G09G2360/128 , G11C7/1042 , H04N5/14 , H04N5/46 , H04N5/7416 , H04N7/012 , H04N7/0132 , H04N21/44004
摘要： Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least two memory devices, each memory device having a plurality of memory locations, where data is stored in parallel to the memory devices and retrieved in parallel from the memory devices, and where data is stored according to the first order using blocks of memory locations, each block having a number of memory locations equal to a power of 2; a first data switch connected to the data source and each of the memory devices, where the first data switch controls which data is stored to which memory device; and a second data switch connected to the data destination and each of the memory devices, where the second data switch controls providing data to the data destination according to the second order.
摘要翻译：用于并行存储数据并以不同顺序检索数据的方法和装置。在一个实现中，用于像素的数据根据棋盘图案交替地存储在两个存储器件之间，形成棋盘缓冲器。在一个实现中，棋盘缓冲器包括：数据源，以第一顺序提供数据; 数据目的地，以二次接收数据; 至少两个存储器设备，每个存储器设备具有多个存储器位置，其中数据与存储器设备并行存储并且从存储器设备并行检索，并且其中根据第一次存储数据使用存储器位置块每个块具有等于2的幂的多个存储器位置; 连接到数据源和每个存储器件的第一数据开关，其中第一数据开关控制将哪个数据存储到哪个存储器件; 以及连接到数据目的地和每个存储设备的第二数据交换机，其中第二数据交换机根据第二顺序控制向数据目的地提供数据。

3. 发明申请

US20080049032A1 CHECKERBOARD BUFFER USING TWO-DIMENSIONAL BUFFER PAGES 失效
标题翻译：使用二维缓冲器页面的检查板缓冲器
公开(公告)号：US20080049032A1
公开(公告)日：2008-02-28
申请号：US11932217
申请日：2007-10-31
申请人： Mark Champion , Brian Dockter
发明人： Mark Champion , Brian Dockter
IPC分类号： G09G5/39
CPC分类号： H04N7/01 , G06T1/60 , G09G5/39 , G09G5/393 , G09G2340/0407 , G09G2352/00 , G09G2360/122 , G09G2360/128 , G11C7/1042 , H04N5/14 , H04N5/46 , H04N5/7416 , H04N7/012 , H04N7/0132
摘要： Methods and apparatus for storing and retrieving data using two-dimensional arrays. In one implementation, a checkerboard buffer page system includes: a data source, providing data elements in a first order; a data destination, receiving data elements in a second order; memory devices having memory pages, data elements stored and retrieved in parallel to and from the memory devices; each buffer page having entries along a first dimension corresponding to the first order and along a second dimension corresponding to the second order, data elements stored in the first order and retrieved in the second order, at least one memory page stores data elements in multiple locations according to the first and second orders, at least two data elements consecutive in the first order are stored in parallel to the memory devices, and where at least two data elements consecutive in the second order are retrieved in parallel from the memories.
摘要翻译：使用二维阵列存储和检索数据的方法和装置。在一个实现中，棋盘缓冲器页面系统包括：数据源，以第一顺序提供数据元素; 数据目的地，以二次接收数据元素; 具有存储器页面的存储器件，与存储器件并行存储和检索的数据元件; 每个缓冲器页面具有沿着与第一顺序对应的第一维度的条目以及沿着与第二顺序对应的第二维度的数据元素，以第一顺序存储并以二次检索的至少一个存储器页面存储多个位置中的数据元素根据第一和第二顺序，以与第一顺序相连的至少两个数据元素与存储器件并行存储，并且其中从存储器并行地检索至少两个以二次连续的数据元素。

4. 发明授权

US07205993B2 Checkerboard buffer using two-dimensional buffer pages and using memory bank alternation 失效
标题翻译：棋盘缓冲区使用二维缓冲页面和使用存储库交替
公开(公告)号：US07205993B2
公开(公告)日：2007-04-17
申请号：US10076943
申请日：2002-02-14
申请人： Mark Champion , Brian Dockter
发明人： Mark Champion , Brian Dockter
IPC分类号： G09G5/399
CPC分类号： H04N7/01 , G06T1/60 , G09G5/399 , G09G2352/00 , G09G2360/123 , G09G2360/128 , G11C7/1042 , H04N5/14 , H04N5/46 , H04N5/7416 , H04N7/012 , H04N7/0132
摘要： Methods and apparatus for storing and retrieving data. In one implementation, a system includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least four memories, each having memory pages, data stored to at least two memories and retrieved from at least two memories in parallel, each buffer page having entries along a first dimension corresponding to the first order and entries along a second dimension corresponding to the second order, data stored in the first order and retrieved in the second order, at least one memory page stores data in multiple locations according to the first and second orders, two data elements consecutive in the first order stored in parallel to the memories, at least two data elements consecutive in the second order retrieved in parallel from the memories.
摘要翻译：用于存储和检索数据的方法和装置。在一个实现中，系统包括：数据源，以第一顺序提供数据; 数据目的地，以二次接收数据; 至少四个存储器，每个具有存储器页面，存储到至少两个存储器并且并行地从至少两个存储器检索的数据，每个缓冲器页面具有沿着与第一顺序相对应的第一维度的条目，以及沿着与第以第二顺序存储的数据并以第二顺序检索，至少一个存储器页根据第一和第二顺序存储多个位置中的数据，以与存储器并行存储的第一顺序连续的两个数据元素，以从存储器中并行检索到的二阶连续的至少两个数据元素。

5. 发明授权

US07088369B2 Checkerboard buffer using two-dimensional buffer pages and using bit-field addressing 失效
公开(公告)号：US07088369B2
公开(公告)日：2006-08-08
申请号：US10076832
申请日：2002-02-14
申请人： Mark Champion , Brian Dockter
发明人： Mark Champion , Brian Dockter
IPC分类号： G09G5/39
CPC分类号： G11C7/1042 , G09G5/39 , G09G5/393 , G09G5/395 , G09G2352/00 , G09G2360/12 , G09G2360/123 , G09G2360/128
摘要： Methods and apparatus for storing and retrieving data. In one implementation, a system includes: a data source, providing data in a first order; a data destination, receiving data in a second order; memory devices having memory pages, data stored in parallel and retrieved in parallel; each buffer page having entries along a first dimension corresponding to the first order and entries along a second dimension corresponding to the second order, data stored according to the first order using blocks of buffer pages, each block having a number of pages equal to a power of 2, data stored in the first order and retrieved in the second order, at least one memory page stores data in multiple locations according to the first and second orders, data elements consecutive in the first order are stored in parallel, data elements consecutive in the second order are retrieved in parallel.

6. 发明申请

US20050057572A1 Checkerboard buffer 失效
标题翻译：棋盘缓冲区
公开(公告)号：US20050057572A1
公开(公告)日：2005-03-17
申请号：US10959535
申请日：2004-10-05
申请人： Mark Champion , Brian Dockter
发明人： Mark Champion , Brian Dockter
IPC分类号： G06T1/60 , G09G3/00 , G09G3/34 , G09G5/39 , G09G5/391 , G09G5/393 , G09G5/395 , G09G5/399 , G11C7/10 , H04N5/14 , H04N5/46 , H04N5/74 , H04N7/01 , H04N21/44 , G09G5/02
CPC分类号： H04N7/01 , G06T1/60 , G09G5/39 , G09G5/399 , G09G2352/00 , G09G2360/123 , G09G2360/128 , G11C7/1042 , H04N5/14 , H04N5/46 , H04N5/7416 , H04N7/012 , H04N7/0132 , H04N21/44004
摘要： Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least two memory devices, each memory device having a plurality of memory locations, where data is stored in parallel to the memory devices and retrieved in parallel from the memory devices; a first data switch connected to the data source and each of the memory devices, where the first data switch controls which data is stored to which memory device; and a second data switch connected to the data destination and each of the memory devices, where the second data switch controls providing data to the data destination according to the second order.
摘要翻译：用于并行存储数据并以不同顺序检索数据的方法和装置。在一个实现中，用于像素的数据根据棋盘图案交替存储在两个存储器件之间，形成棋盘缓冲器。在一个实现中，棋盘缓冲器包括：数据源，以第一顺序提供数据; 数据目的地，以二次接收数据; 至少两个存储器设备，每个存储器设备具有多个存储器位置，其中数据与存储器设备并行存储并且从存储器设备并行检索; 连接到数据源和每个存储器件的第一数据开关，其中第一数据开关控制将哪个数据存储到哪个存储器件; 以及连接到数据目的地和每个存储设备的第二数据交换机，其中第二数据交换机根据第二级控制向数据目的地提供数据。

7. 发明授权

US06803917B2 Checkerboard buffer using memory bank alternation 有权
标题翻译：使用存储库交替的棋盘缓冲区
公开(公告)号：US06803917B2
公开(公告)日：2004-10-12
申请号：US09908301
申请日：2001-07-17
申请人： Mark Champion , Brian Dockter
发明人： Mark Champion , Brian Dockter
IPC分类号： G09G5399
CPC分类号： H04N7/01 , G06T1/60 , G09G5/39 , G09G5/399 , G09G2352/00 , G09G2360/123 , G09G2360/128 , G11C7/1042 , H04N5/14 , H04N5/46 , H04N5/7416 , H04N7/012 , H04N7/0132 , H04N21/44004
摘要： Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels for one frame is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. While data is being stored, data for pixels from another frame is retrieved from another two memory devices. The banks of devices alternate between storing and retrieving with each frame. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least four memory devices, each memory device having a plurality of memory locations, where data is stored in parallel to at least two memory devices and retrieved in parallel from at least two memory devices; a first data switch connected to the data source and each of the memory devices, where the first data switch controls which data is stored to which memory device; and a second data switch connected to the data destination and each of the memory devices, where the second data switch controls providing data to the data destination according to the second order.
摘要翻译：用于并行存储数据并以不同顺序检索数据的方法和装置。在一个实现中，一帧的像素的数据根据棋盘图案交替地存储在两个存储器件之间，形成棋盘缓冲器。当存储数据时，从另外两个存储器件检索来自另一帧的像素的数据。设备库在每个帧之间交替存储和检索。在一个实现中，棋盘缓冲器包括：数据源，以第一顺序提供数据; 数据目的地，以二次接收数据; 至少四个存储器设备，每个存储器设备具有多个存储器位置，其中数据与至少两个存储器设备并行存储并且从至少两个存储器设备并行检索; 连接到数据源和每个存储器件的第一数据开关，其中第一数据开关控制将哪个数据存储到哪个存储器件; 以及连接到数据目的地和每个存储设备的第二数据交换机，其中第二数据交换机根据第二级控制向数据目的地提供数据。

8. 发明授权

US07830391B2 Checkerboard buffer using two-dimensional buffer pages 失效
标题翻译：棋盘缓冲区使用二维缓冲页面
公开(公告)号：US07830391B2
公开(公告)日：2010-11-09
申请号：US11932217
申请日：2007-10-31
申请人： Mark Champion , Brian Dockter
发明人： Mark Champion , Brian Dockter
IPC分类号： G06F13/00 , G09G5/399 , G09G5/36 , G09G5/39
CPC分类号： H04N7/01 , G06T1/60 , G09G5/39 , G09G5/393 , G09G2340/0407 , G09G2352/00 , G09G2360/122 , G09G2360/128 , G11C7/1042 , H04N5/14 , H04N5/46 , H04N5/7416 , H04N7/012 , H04N7/0132
摘要： Methods and apparatus for storing and retrieving data using two-dimensional arrays. In one implementation, a checkerboard buffer page system includes: a data source, providing data elements in a first order; a data destination, receiving data elements in a second order; memory devices having memory pages, data elements stored and retrieved in parallel to and from the memory devices; each buffer page having entries along a first dimension corresponding to the first order and along a second dimension corresponding to the second order, data elements stored in the first order and retrieved in the second order, at least one memory page stores data elements in multiple locations according to the first and second orders, at least two data elements consecutive in the first order are stored in parallel to the memory devices, and where at least two data elements consecutive in the second order are retrieved in parallel from the memories.
摘要翻译：使用二维阵列存储和检索数据的方法和装置。在一个实现中，棋盘缓冲器页面系统包括：数据源，以第一顺序提供数据元素; 数据目的地，以二次接收数据元素; 具有存储器页面的存储器件，与存储器件并行存储和检索的数据元件; 每个缓冲器页面具有沿着与第一顺序对应的第一维度的条目以及沿着与第二顺序对应的第二维度的数据元素，以第一顺序存储并以二次检索的至少一个存储器页面将数据元素存储在多个位置根据第一和第二顺序，以与第一顺序相连的至少两个数据元素与存储器件并行存储，并且其中从存储器并行地检索至少两个以二次连续的数据元素。

9. 发明授权

US07379069B2 Checkerboard buffer using two-dimensional buffer pages 失效
标题翻译：棋盘缓冲区使用二维缓冲页面
公开(公告)号：US07379069B2
公开(公告)日：2008-05-27
申请号：US10076685
申请日：2002-02-14
申请人： Mark Champion , Brian Dockter
发明人： Mark Champion , Brian Dockter
IPC分类号： G06F13/00 , G09G5/36 , G09G5/39
CPC分类号： H04N7/01 , G06T1/60 , G09G5/39 , G09G5/393 , G09G2340/0407 , G09G2352/00 , G09G2360/122 , G09G2360/128 , G11C7/1042 , H04N5/14 , H04N5/46 , H04N5/7416 , H04N7/012 , H04N7/0132
摘要： Methods and apparatus for storing and retrieving data using two-dimensional arrays. In one implementation, a checkerboard buffer page system includes: a data source, providing data elements in a first order; a data destination, receiving data elements in a second order; memory devices having memory pages, data elements stored and retrieved in parallel to and from the memory devices; each buffer page having entries along a first dimension corresponding to the first order and along a second dimension corresponding to the second order, data elements stored in the first order and retrieved in the second order, at least one memory page stores data elements in multiple locations according to the first and second orders, at least two data elements consecutive in the first order are stored in parallel to the memory devices, and where at least two data elements consecutive in the second order are retrieved in parallel from the memories.
摘要翻译：使用二维阵列存储和检索数据的方法和装置。在一个实现中，棋盘缓冲器页面系统包括：数据源，以第一顺序提供数据元素; 数据目的地，以二次接收数据元素; 具有存储器页面的存储器件，与存储器件并行存储和检索的数据元件; 每个缓冲器页面具有沿着与第一顺序对应的第一维度的条目以及沿着与第二顺序对应的第二维度的数据元素，以第一顺序存储并以二次检索的至少一个存储器页面将数据元素存储在多个位置根据第一和第二顺序，以与第一顺序相连的至少两个数据元素与存储器件并行存储，并且其中从存储器并行地检索至少两个以二次连续的数据元素。

10. 发明授权

US06831650B2 Checkerboard buffer using sequential memory locations 有权
标题翻译：棋盘缓冲区使用顺序存储位置
公开(公告)号：US06831650B2
公开(公告)日：2004-12-14
申请号：US09907852
申请日：2001-07-17
申请人： Mark Champion , Brian Dockter
发明人： Mark Champion , Brian Dockter
IPC分类号： G09G5399
CPC分类号： H04N7/01 , G06T1/60 , G09G5/39 , G09G5/399 , G09G2352/00 , G09G2360/123 , G09G2360/128 , G11C7/1042 , H04N5/14 , H04N5/46 , H04N5/7416 , H04N7/012 , H04N7/0132 , H04N21/44004
摘要： Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least two memory devices, each memory device having a plurality of memory locations, where data is stored in parallel to the memory devices and retrieved in parallel from the memory devices, and where data is stored according to the first order using sequential memory locations in the memory devices; a first data switch connected to the data source and each of the memory devices, where the first data switch controls which data is stored to which memory device; and a second data switch connected to the data destination and each of the memory devices, where the second data switch controls providing data to the data destination according to the second order.
摘要翻译：用于并行存储数据并以不同顺序检索数据的方法和装置。在一个实现中，用于像素的数据根据棋盘图案交替存储在两个存储器件之间，形成棋盘缓冲器。在一个实现中，棋盘缓冲器包括：数据源，以第一顺序提供数据; 数据目的地，以二次接收数据; 至少两个存储器设备，每个存储器设备具有多个存储器位置，其中数据与存储器设备并行存储并且从存储器设备并行检索，并且其中根据第一顺序存储数据，使用顺序存储器位置存储器件; 连接到数据源和每个存储器件的第一数据开关，其中第一数据开关控制将哪个数据存储到哪个存储器件; 以及连接到数据目的地和每个存储设备的第二数据交换机，其中第二数据交换机根据第二级控制向数据目的地提供数据。

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