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1. 发明授权

US07437650B2 Pre-emptive interleaver address generator for turbo decoders 有权
标题翻译： turbo解码器的抢占交织器地址发生器
公开(公告)号：US07437650B2
公开(公告)日：2008-10-14
申请号：US11103489
申请日：2005-04-12
申请人： Mark Andrew Bickerstaff , Yi-Chen Li , Chris Nicol , Bejamin John Widdup
发明人： Mark Andrew Bickerstaff , Yi-Chen Li , Chris Nicol , Bejamin John Widdup
IPC分类号： H03M13/27 , H03M13/29
CPC分类号： H03M13/2775 , H03M13/2714 , H03M13/276 , H03M13/2771 , H03M13/6516 , H03M13/6519
摘要： An interleaver address generator is provided with pruning avoidance technology. It anticipates the points in time when incorrect addresses are computed by an IAG, and bypasses these events. It produces a stream of valid, contiguous addresses for all specified code block sizes. A single address computation engine firstly ‘trains’ itself about violating generated addresses (for a related block size) during the initial H1 half-iteration of decoder operation, and then produces a continuous, correct stream of addresses as required by the turbo decoder. Thus regions of pruned addresses are determined, and then training is performed only in these regions. Thus, computation and population of a pruned event table is determined in less than 1/10 the time required to do a conventional style full training. The resulting pruned event table is compressed down to 256 bits.
摘要翻译：交织器地址发生器具有修剪避免技术。它预计在IAG计算不正确地址的时间点，并绕过这些事件。它为所有指定的代码块大小生成一个有效，连续的地址流。单个地址计算引擎首先在解码器操作的初始H1半迭代期间“违反”生成的地址（对于相关块大小）进行“训练”，然后根据turbo解码器的要求产生连续的正确的地址流。因此，确定了修剪地址的区域，然后仅在这些区域中执行训练。因此，修剪事件表的计算和人口在不到传统风格完全训练所需时间的1/10内确定。生成的修剪事件表被压缩到256位。

2. 发明申请

US20060242476A1 Pre-emptive interleaver address generator for turbo decoders 有权
标题翻译： turbo解码器的抢占交织器地址发生器
公开(公告)号：US20060242476A1
公开(公告)日：2006-10-26
申请号：US11103489
申请日：2005-04-12
申请人： Mark Bickerstaff , Yi-Chen Li , Chris Nicol , Bejamin Widdup
发明人： Mark Bickerstaff , Yi-Chen Li , Chris Nicol , Bejamin Widdup
IPC分类号： G11C29/00
CPC分类号： H03M13/2775 , H03M13/2714 , H03M13/276 , H03M13/2771 , H03M13/6516 , H03M13/6519
摘要： An interleaver address generator is provided with pruning avoidance technology. It anticipates the points in time when incorrect addresses are computed by an IAG, and bypasses these events. It produces a stream of valid, contiguous addresses for all specified code block sizes. A single address computation engine firstly ‘trains’ itself about violating generated addresses (for a related block size) during the initial H1 half-iteration of decoder operation, and then produces a continuous, correct stream of addresses as required by the turbo decoder. Thus regions of pruned addresses are determined, and then training is performed only in these regions. Thus, computation and population of a pruned event table is determined in less than 1/10 the time required to do a conventional style full training. The resulting pruned event table is compressed down to 256 bits.
摘要翻译：交织器地址发生器具有修剪避免技术。它预计在IAG计算不正确地址的时间点，并绕过这些事件。它为所有指定的代码块大小生成一个有效，连续的地址流。单个地址计算引擎首先在解码器操作的初始H1半迭代期间“违反”生成的地址（对于相关块大小）进行“训练”，然后根据turbo解码器的要求产生连续的正确的地址流。因此，确定了修剪地址的区域，然后仅在这些区域中执行训练。因此，修剪事件表的计算和人口在不到传统风格完全训练所需时间的1/10内确定。生成的修剪事件表被压缩到256位。

3. 发明授权

US07974997B2 Hardware matrix computation for wireless receivers 有权
标题翻译：无线接收机的硬件矩阵计算
公开(公告)号：US07974997B2
公开(公告)日：2011-07-05
申请号：US11731174
申请日：2007-03-30
申请人： Eliahou Arviv , Robert L. Lang , Yi-Chen Li , Oliver Ridler , Xiao-an Wang
发明人： Eliahou Arviv , Robert L. Lang , Yi-Chen Li , Oliver Ridler , Xiao-an Wang
IPC分类号： G06F17/16
CPC分类号： G06F17/16 , H04B1/707 , H04B2201/70707 , H04B2201/709727
摘要： In one embodiment, a receiver including one or more signal-processing blocks and a hardware-based matrix co-processor. The one or more signal-processing blocks are adapted to generate a processed signal from a received signal. The hardware-based matrix co-processor includes two or more different matrix-computation engines, each adapted to perform a different matrix computation, and one or more shared hardware-computation units, each adapted to perform a mathematical operation. At least one signal-processing block is adapted to offload matrix-based signal processing to the hardware-based matrix co-processor. Each of the two or more different matrix-computation engines is adapted to offload the same type of mathematical processing to at least one of the one or more shared hardware-computation units.
摘要翻译：在一个实施例中，接收机包括一个或多个信号处理块和基于硬件的矩阵协处理器。所述一个或多个信号处理块适于从接收到的信号产生经处理的信号。基于硬件的矩阵协处理器包括两个或更多个不同的矩阵计算引擎，每个矩阵计算引擎适于执行不同的矩阵计算，以及一个或多个共享硬件计算单元，每个共享硬件计算单元适于执行数学运算。至少一个信号处理块适于将基于矩阵的信号处理卸载到基于硬件的矩阵协处理器。两个或更多个不同的矩阵计算引擎中的每一个适于将相同类型的数学处理卸载到一个或多个共享硬件计算单元中的至少一个。

4. 发明申请

US20090296798A1 HSDPA CO-PROCESSOR FOR MOBILE TERMINALS 审中-公开
标题翻译：用于移动终端的HSDPA CO处理器
公开(公告)号：US20090296798A1
公开(公告)日：2009-12-03
申请号：US12295683
申请日：2007-04-05
申请人： Rami Banna , Mark A. Bickerstaff , Matthew E. Cooke , Adriel P. kind , Yi-Chen Li , Oliver Ridler , Uwe Sontowski , Charles N. A. Thomas , Long Ung , Koen Van den Beld , Benjamin J. Widdup , Graeme K. Woodward , Dominic Wing-Kin Yip , Gongyu Zhou
发明人： Rami Banna , Mark A. Bickerstaff , Matthew E. Cooke , Adriel P. kind , Yi-Chen Li , Oliver Ridler , Uwe Sontowski , Charles N. A. Thomas , Long Ung , Koen Van den Beld , Benjamin J. Widdup , Graeme K. Woodward , Dominic Wing-Kin Yip , Gongyu Zhou
IPC分类号： H03H7/40 , H04W4/00
CPC分类号： H04B1/70754 , H04B1/7097 , H04B2201/70701 , H04L25/03057 , H04L25/03292 , H04L2025/03617 , H04L2025/03687
摘要： In one embodiment, an HSDPA co-processor for 3GPP Release 6 Category 8 (7.2 Mb/s) HSDPA that provides all chip-rate, symbol-rate, physical-channel, and transport-channel processing for HSDPA in 90 nm CMOS. The co-processor design is scalable to all HSDPA data rates up to 14 Mb/s. The coprocessor implements an Advanced Receiver based on an NLMS equalizer, supports RX diversity and TX diversity, and provides up to 6.4 dB better performance than a typical single-antenna rake receiver. Thus, 3GPP R6 HSDPA functionality can be added to a legacy R99 modem using an HSDPA co-processor consistent with embodiments of the present invention, at a reasonable incremental cost and power.
摘要翻译：在一个实施例中，用于3GPP版本6类别（7.2Mb / s）HSDPA的HSDPA协处理器为90nm CMOS中的HSDPA提供所有芯片速率，符号速率，物理信道和传输信道处理。协处理器设计可扩展到高达14 Mb / s的所有HSDPA数据速率。协处理器基于NLMS均衡器实现高级接收机，支持RX分集和TX分集，并且比典型的单天线耙式接收机提供高达6.4 dB的性能。因此，3GPP R6 HSDPA功能可以以合理的增量成本和功率被添加到与本发明实施例一致的HSDPA协处理器的传统R99调制解调器。

5. 发明申请

US20080243982A1 Hardware matrix computation for wireless receivers 有权
标题翻译：无线接收机的硬件矩阵计算
公开(公告)号：US20080243982A1
公开(公告)日：2008-10-02
申请号：US11731174
申请日：2007-03-30
申请人： Eliahou Arviv , Robert L. Lang , Yi-Chen Li , Oliver Ridler , Xiao-an Wang
发明人： Eliahou Arviv , Robert L. Lang , Yi-Chen Li , Oliver Ridler , Xiao-an Wang
IPC分类号： G06F17/10 , G06F7/32
CPC分类号： G06F17/16 , H04B1/707 , H04B2201/70707 , H04B2201/709727
摘要： In one embodiment, a receiver including one or more signal-processing blocks and a hardware-based matrix co-processor. The one or more signal-processing blocks are adapted to generate a processed signal from a received signal. The hardware-based matrix co-processor includes two or more different matrix-computation engines, each adapted to perform a different matrix computation, and one or more shared hardware-computation units, each adapted to perform a mathematical operation. At least one signal-processing block is adapted to offload matrix-based signal processing to the hardware-based matrix co-processor. Each of the two or more different matrix-computation engines is adapted to offload the same type of mathematical processing to at least one of the one or more shared hardware-computation units.
摘要翻译：在一个实施例中，接收机包括一个或多个信号处理块和基于硬件的矩阵协处理器。所述一个或多个信号处理块适于从接收到的信号产生经处理的信号。基于硬件的矩阵协处理器包括两个或更多个不同的矩阵计算引擎，每个矩阵计算引擎适于执行不同的矩阵计算，以及一个或多个共享硬件计算单元，每个共享硬件计算单元适于执行数学运算。至少一个信号处理块适于将基于矩阵的信号处理卸载到基于硬件的矩阵协处理器。两个或更多个不同的矩阵计算引擎中的每一个适于将相同类型的数学处理卸载到一个或多个共享硬件计算单元中的至少一个。

6. 发明授权

US08955315B2 Hydroelectric generator 有权
标题翻译：水力发电机
公开(公告)号：US08955315B2
公开(公告)日：2015-02-17
申请号：US13241782
申请日：2011-09-23
申请人： Chih-Wei Yen , Yi-Chen Li , Tzu-Hung Huang , Yin-Ling Kuo
发明人： Chih-Wei Yen , Yi-Chen Li , Tzu-Hung Huang , Yin-Ling Kuo
IPC分类号： F16D31/02 , F03D3/00 , F03D11/00 , F03B13/26
CPC分类号： F03B13/264 , F05B2240/133 , F05B2240/97 , Y02E10/28 , Y02E10/38 , Y10S415/914
摘要： A hydroelectric generator includes a body and an electromechanical apparatus cabin. The body has a tube penetrating the body and a first flow channel. The tube has a tapering segment and a throat portion communicating with the first tapering segment. One end portion of the first flow channel is located on a wall surface of the throat portion, so that the first flow channel communicates with the tube. The first flow channel is used to enable a fluid to flow into the tube from the first flow channel or guide a fluid to flow out of the body from the throat portion. The electromechanical apparatus cabin has an energy retrieving apparatus disposed in the throat portion of the tube, and the end portion of the first flow channel communicating with the tube is located at a front side or a back side of the energy retrieving apparatus.
摘要翻译：水力发电机包括主体和机电装置舱。身体具有穿透身体的管和第一流动通道。管具有锥形段和与第一锥形段连通的喉部。第一流路的一端部位于喉部的壁面上，使第一流路与管连通。第一流动通道用于使流体能够从第一流动通道流入管中或引导流体从喉部部分流出身体。机电装置舱具有设置在管的喉部的能量回收装置，与管连通的第一流路的端部位于能量回收装置的前侧或后侧。

7. 发明授权

US07352723B2 Method of forming a coded composite transport channel for downlink transmissions 有权
标题翻译：形成用于下行链路传输的编码复合传输信道的方法
公开(公告)号：US07352723B2
公开(公告)日：2008-04-01
申请号：US10422838
申请日：2003-04-25
申请人： Mark Barry , Hettiachchi Upul Gunawardana , Yi-Chen Li , Koen van den Beld
发明人： Mark Barry , Hettiachchi Upul Gunawardana , Yi-Chen Li , Koen van den Beld
IPC分类号： H04B7/216
CPC分类号： H04L1/0071
摘要： In a communication method, data from a plurality of channels is combined into a composite channel by writing data from the plurality of channels as one-bit symbols to a memory, and reading out the data from memory to form the composite channel. The combining of radio frames from the channels forms a coded composite transport channel for transmitting the data in the downlink. To form the coded composite transport channel, an input process is initiated to write data for each radio frame of a transport channel as one bit symbols to a memory of an interleaver. On an output side of the interleaver, an output process to read out the data stored in the memory is performed to form the coded composite transport channel.
摘要翻译：在通信方法中，通过将来自多个信道的数据作为1比特符号写入到存储器中，将来自多个信道的数据组合成复合信道，并从存储器读出数据以形成复合信道。来自信道的无线帧的组合形成用于在下行链路中发送数据的编码复合传输信道。为了形成编码的复合传输信道，启动输入处理以将传输信道的每个无线电帧的数据作为一个比特符号写入交织器的存储器。在交织器的输出侧，执行用于读出存储在存储器中的数据的输出处理，以形成编码的复合传输信道。

8. 发明授权

US08218298B2 Door mechanism with a retractable function and related electronic device 有权
标题翻译：具有伸缩功能和相关电子设备的门机构
公开(公告)号：US08218298B2
公开(公告)日：2012-07-10
申请号：US12828250
申请日：2010-06-30
申请人： Yu-Han Tsai , Chun-Wang Lin , Yu-Hsien Huang , Yi-Chen Li , Chi-Jen Lo , Feng-Hsiung Wu
发明人： Yu-Han Tsai , Chun-Wang Lin , Yu-Hsien Huang , Yi-Chen Li , Chi-Jen Lo , Feng-Hsiung Wu
IPC分类号： H05K5/00 , H05K7/00
CPC分类号： E05C3/10 , E05B15/101 , E05C3/048 , G06F1/1656
摘要： A door mechanism includes a main body whereon an opening is formed. The main body is for shielding a slot on a casing of an electronic device. The door mechanism further includes a first resilient component. One end of the first resilient component is fixed inside the main body. The door mechanism further includes a shaft including a pivoting portion pivoted to the casing of the electronic device so that the main body is capable of rotating relative to the casing. The shaft further includes an extending portion. One end of the extending portion is connected to the pivoting portion, and the other end of the extending portion passes through the opening and is connected to the other end of the first resilient component. The main body is capable of moving relative to the pivoting portion due to deformation of the first resilient component.
摘要翻译：门机构包括形成开口的主体。主体用于屏蔽电子设备外壳上的槽。门机构还包括第一弹性部件。第一弹性部件的一端固定在主体内。门机构还包括轴，其包括枢转到电子设备的壳体的枢转部分，使得主体能够相对于壳体旋转。轴还包括延伸部分。延伸部分的一端连接到枢转部分，并且延伸部分的另一端穿过开口并连接到第一弹性部件的另一端。由于第一弹性部件的变形，主体能够相对于枢转部移动。

9. 发明申请

US20110141669A1 DOOR MECHANISM WITH A RETRACTABLE FUNCTION AND RELATED ELECTRONIC DEVICE 有权
标题翻译：具有可恢复功能的门机构及相关电子设备
公开(公告)号：US20110141669A1
公开(公告)日：2011-06-16
申请号：US12828250
申请日：2010-06-30
申请人： Yu-Han Tsai , Chun-Wang Lin , Yu-Hsien Huang , Yi-Chen Li , Chi-Jen Lo , Feng-Hsiung Wu
发明人： Yu-Han Tsai , Chun-Wang Lin , Yu-Hsien Huang , Yi-Chen Li , Chi-Jen Lo , Feng-Hsiung Wu
IPC分类号： H05K7/00 , E05F1/10 , E05B65/06
CPC分类号： E05C3/10 , E05B15/101 , E05C3/048 , G06F1/1656
摘要： A door mechanism includes a main body whereon an opening is formed. The main body is for shielding a slot on a casing of an electronic device. The door mechanism further includes a first resilient component. One end of the first resilient component is fixed inside the main body. The door mechanism further includes a shaft including a pivoting portion pivoted to the casing of the electronic device so that the main body is capable of rotating relative to the casing. The shaft further includes an extending portion. One end of the extending portion is connected to the pivoting portion, and the other end of the extending portion passes through the opening and is connected to the other end of the first resilient component. The main body is capable of moving relative to the pivoting portion due to deformation of the first resilient component.
摘要翻译：门机构包括形成开口的主体。主体用于屏蔽电子设备外壳上的槽。门机构还包括第一弹性部件。第一弹性部件的一端固定在主体内。门机构还包括轴，其包括枢转到电子设备的壳体的枢转部分，使得主体能够相对于壳体旋转。轴还包括延伸部分。延伸部分的一端连接到枢转部分，并且延伸部分的另一端穿过开口并连接到第一弹性部件的另一端。由于第一弹性部件的变形，主体能够相对于枢转部移动。

10. 发明申请

US20070266302A1 Method and apparatus for dedicated hardware and software split implementation of rate matching and de-matching 审中-公开
公开(公告)号：US20070266302A1
公开(公告)日：2007-11-15
申请号：US11826900
申请日：2007-07-19
申请人： Mark Barry , Yi-Chen Li , Oliver Ridler
发明人： Mark Barry , Yi-Chen Li , Oliver Ridler
IPC分类号： H03M13/03
CPC分类号： H04L1/0067 , H04L1/0043 , H04L1/0045 , H04L1/0059 , H04L1/0066 , H04L1/0069 , H04L1/0071 , H04L1/08
摘要： In the method of rate-matching, software is used to calculate at least one rate-matching parameter for data, and dedicated hardware is used to perform at least one of a puncturing and repetition process on data based on the calculated rate-matching parameter. In rate de-matching, software is again used to calculate at least one rate de-matching parameter for received data, and dedicated hardware is used to compensate for puncturing and repetition based on the calculated rate de-matching parameter.

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