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1. 发明授权

US07135123B1 Method and system for integrated circuit backside navigation 失效
标题翻译：集成电路背面导航的方法和系统
公开(公告)号：US07135123B1
公开(公告)日：2006-11-14
申请号：US10758146
申请日：2004-01-14
申请人： Mark Alan Thompson , Erwan Le Roy , Theodore Lundquist , William B. Thompson , Catherine Kardach
发明人： Mark Alan Thompson , Erwan Le Roy , Theodore Lundquist , William B. Thompson , Catherine Kardach
IPC分类号： G01L21/30 , H01L21/00
CPC分类号： G01R31/2898 , G01R31/307 , H01L21/3043 , H01L23/544 , H01L2924/0002 , H01L2924/00
摘要： The backside navigation method of the present invention includes milling a fiducial opening through the substrate of an integrated circuit. The milling process is stopped when the fiducial opening reaches the bottom of a trench isolation structure. The trench isolation structure delineated by the fiducial opening may be imaged and registered to a computer aided design layout image to achieve sub-micron navigation resolution.
摘要翻译：本发明的背面导航方法包括通过集成电路的基板铣削基准开口。当基准开口到达沟槽隔离结构的底部时，铣削过程停止。由基准开口划定的沟槽隔离结构可以被成像并记录到计算机辅助设计布局图像中以实现亚微米导航分辨率。

2. 发明申请

US20070293052A1 APPARATUS AND METHOD FOR OPTICAL INTERFERENCE FRINGE BASED INTEGRATED CIRCUIT PROCESSING 有权
标题翻译：基于光干扰法的基于集成电路处理的装置和方法
公开(公告)号：US20070293052A1
公开(公告)日：2007-12-20
申请号：US11754466
申请日：2007-05-29
申请人： Erwan Le Roy , Chun-Cheng Tsao , Theodore Lundquist , Rajesh Jain
发明人： Erwan Le Roy , Chun-Cheng Tsao , Theodore Lundquist , Rajesh Jain
IPC分类号： H01L21/302
CPC分类号： H01L21/3065 , H01J37/228 , H01J37/3056 , H01J2237/2482 , H01J2237/30466 , H01J2237/31749 , H01L22/12 , H01L22/26
摘要： An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, one or more wavelength lights are directed on the integrated circuit and based upon the detection of interference fringes and characteristics of the same, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection and/or characteristics of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Resulting fringes will be a function, in part, of the thickness and/or profile of the trench floor. Milling may be controlled as a function of the detected fringe patterns.
摘要翻译：一种使用光学干涉条纹处理集成电路的装置和方法。在处理期间，一个或多个波长的光被引导到集成电路上，并且基于干涉条纹和其特性的检测，可以控制进一步的处理。一种实施方案涉及集成电路的带电粒子束处理，作为干涉条纹的检测和/或特征的函数。在集成电路的衬底中或其上执行带电粒子束沟槽铣削操作。光线指向沟槽的地板。干涉条纹可以由从地板反射的光与来自电路结构的光之间的建构性或破坏性干扰形成。所产生的条纹将部分地是沟槽地板的厚度和/或轮廓的函数。作为检测到的条纹图案的函数可以控制铣削。

3. 发明授权

US07488937B2 Method and apparatus for the improvement of material/voltage contrast 有权
标题翻译：用于改善材料/电压对比度的方法和装置
公开(公告)号：US07488937B2
公开(公告)日：2009-02-10
申请号：US11252139
申请日：2005-10-17
申请人： Erwan Le Roy , William B. Thompson
发明人： Erwan Le Roy , William B. Thompson
IPC分类号： H01L21/00
CPC分类号： H01L21/31608 , G01N23/2251 , G01R31/307 , H01J37/3005 , H01J37/3056 , H01J2237/30466 , H01J2237/3174 , H01J2237/31749 , H01L21/02164 , H01L21/02214 , H01L21/02348 , H01L22/12 , H01L22/26 , H01L22/34 , H01L2924/0002 , Y10T29/41 , H01L2924/00
摘要： A method and system for registering a CAD layout to a Focused Ion Beam image for through-the substrate probing, without using an optical image and without requiring biasing, includes an improved method of trench endpointing during the FIB milling operation with a low beam energy. The method further includes removal of Ga at the trench floor using XeF2, as well as the deposition of an insulating layer onto the trench floor.
摘要翻译：用于将聚焦离子束图像注册到聚焦离子束图像以用于通过基板探测而不使用光学图像并且不需要偏置的方法和系统包括在具有低光束能量的FIB铣削操作期间的沟槽终点的改进方法。该方法还包括使用XeF2在沟槽底板处去除Ga，以及在沟槽地板上沉积绝缘层。

4. 发明授权

US07115426B2 Method and apparatus for addressing thickness variations of a trench floor formed in a semiconductor substrate 有权
公开(公告)号：US07115426B2
公开(公告)日：2006-10-03
申请号：US11031423
申请日：2005-01-07
申请人： Erwan Le Roy , Patricia Le Coupanec , Theodore R. Lundquist , William B. Thompson , Mark A. Thompson , Lokesh Johri
发明人： Erwan Le Roy , Patricia Le Coupanec , Theodore R. Lundquist , William B. Thompson , Mark A. Thompson , Lokesh Johri
IPC分类号： H01L21/66
CPC分类号： H01L22/12
摘要： A method for utilizing interference fringe patterns generated when milling a trench through a semiconductor substrate by a method such as FIB milling, to determine and optimize the thickness uniformity of the trench bottom. The interference fringes may be mapped and the mapping used to direct the FIB milling to those regions which are thicker to correct observed non-uniformities in the trench floor thickness by varying the pixel dwell time across the milled area. The interference fringe mapping may be used to develop computerized contour lines to automate the pixel dwell time variations as described above, for correcting non-uniformities in the trench floor thickness. The method may be applied to applications other than trench formation for backside editing, such as monitoring progress in forming a milled object.

5. 发明授权

US06958248B1 Method and apparatus for the improvement of material/voltage contrast 失效
标题翻译：用于改善材料/电压对比度的方法和装置
公开(公告)号：US06958248B1
公开(公告)日：2005-10-25
申请号：US10789336
申请日：2004-02-27
申请人： Erwan Le Roy , William B. Thompson
发明人： Erwan Le Roy , William B. Thompson
IPC分类号： G01R31/26 , H01J37/305 , H01L21/316 , H01L21/66
CPC分类号： H01L21/31608 , G01N23/2251 , G01R31/307 , H01J37/3005 , H01J37/3056 , H01J2237/30466 , H01J2237/3174 , H01J2237/31749 , H01L21/02164 , H01L21/02214 , H01L21/02348 , H01L22/12 , H01L22/26 , H01L22/34 , H01L2924/0002 , Y10T29/41 , H01L2924/00
摘要： A method and system for registering a CAD layout to a Focused Ion Beam image for through-the substrate probing, without using an optical image and without requiring biasing, includes an improved method of trench endpointing during the FIB milling operation with a low beam energy. The method further includes removal of Ga at the trench floor using XeF2, as well as the deposition of an insulating layer onto the trench floor.
摘要翻译：用于将聚焦离子束图像注册到聚焦离子束图像以用于通过基板探测而不使用光学图像并且不需要偏置的方法和系统包括在具有低光束能量的FIB铣削操作期间的沟槽终点的改进方法。该方法还包括使用XeF 2在沟槽底板处移除Ga以及在沟槽底板上沉积绝缘层。

6. 发明授权

US07036109B1 Imaging integrated circuits with focused ion beam 有权
标题翻译：具有聚焦离子束的成像集成电路
公开(公告)号：US07036109B1
公开(公告)日：2006-04-25
申请号：US10274431
申请日：2002-10-17
申请人： Chun-Cheng Tsao , Theodore R. Lundquist , William Thompson , Erwan Le Roy , Eugene A. Delenia
发明人： Chun-Cheng Tsao , Theodore R. Lundquist , William Thompson , Erwan Le Roy , Eugene A. Delenia
IPC分类号： G06F17/50
CPC分类号： H01J37/3056 , H01J2237/3174
摘要： Methods and apparatus for integrated circuit diagnosis, characterization or modification using a focused ion beam. A method for editing an integrated circuit includes acquiring an image of structures of an integrated circuit by applying a focused ion beam to an outer surface of the integrated circuit to visualize structures beneath the outer surface of the integrated circuit. The method includes using the image to find a location of a circuit element in the integrated circuit and then performing one or more editing operations on the circuit element by applying a focused ion beam to the location found.
摘要翻译：使用聚焦离子束进行集成电路诊断，表征或修改的方法和装置。一种用于编辑集成电路的方法包括通过将集中的离子束施加到集成电路的外表面来获取集成电路的结构图像，以便可视化集成电路外表面下方的结构。该方法包括使用图像来找到集成电路中的电路元件的位置，然后通过将聚焦离子束施加到所找到的位置来对电路元件执行一个或多个编辑操作。

7. 发明申请

US20070087572A1 Method and apparatus for the improvement of material/voltage contrast 审中-公开
标题翻译：用于改善材料/电压对比度的方法和装置
公开(公告)号：US20070087572A1
公开(公告)日：2007-04-19
申请号：US11527434
申请日：2006-09-26
申请人： Erwan Le Roy , Mark Thompson , William Thompson
发明人： Erwan Le Roy , Mark Thompson , William Thompson
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01J37/3056 , H01J37/3005
摘要： A method for observing voltage contrast from buried structures in SOI. The method includes depositing a thin transparent metal layer over the BOx to dissipate charging of the oxide, and using a low FIB beam current to avoid damage due to ion implantation and direct ion beam damage.
摘要翻译：一种用于观察SOI中埋置结构的电压对比度的方法。该方法包括在BOx上沉积薄的透明金属层以消散氧化物的充电，并且使用低FIB束电流以避免由于离子注入和直接离子束损伤而造成的损坏。

8. 发明授权

US07884024B2 Apparatus and method for optical interference fringe based integrated circuit processing 有权
标题翻译：用于光干涉条纹集成电路处理的装置和方法
公开(公告)号：US07884024B2
公开(公告)日：2011-02-08
申请号：US11754466
申请日：2007-05-29
申请人： Erwan Le Roy , Chun-Cheng Tsao , Theodore R. Lundquist , Rajesh Kumar Jain
发明人： Erwan Le Roy , Chun-Cheng Tsao , Theodore R. Lundquist , Rajesh Kumar Jain
IPC分类号： H01L21/302
CPC分类号： H01L21/3065 , H01J37/228 , H01J37/3056 , H01J2237/2482 , H01J2237/30466 , H01J2237/31749 , H01L22/12 , H01L22/26
摘要： An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, one or more wavelength lights are directed on the integrated circuit and based upon the detection of interference fringes and characteristics of the same, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection and/or characteristics of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Resulting fringes will be a function, in part, of the thickness and/or profile of the trench floor. Milling may be controlled as a function of the detected fringe patterns.
摘要翻译：一种使用光学干涉条纹处理集成电路的装置和方法。在处理期间，一个或多个波长的光被引导到集成电路上，并且基于干涉条纹和其特性的检测，可以控制进一步的处理。一种实施方案涉及集成电路的带电粒子束处理，作为干涉条纹的检测和/或特征的函数。在集成电路的衬底中或其上执行带电粒子束沟槽铣削操作。光线指向沟槽的地板。干涉条纹可以由从地板反射的光与来自电路结构的光之间的建构性或破坏性干扰形成。所产生的条纹将部分地是沟槽地板的厚度和/或轮廓的函数。作为检测到的条纹图案的函数可以控制铣削。

9. 发明授权

US07697146B2 Apparatus and method for optical interference fringe based integrated circuit processing 有权
标题翻译：用于光干涉条纹集成电路处理的装置和方法
公开(公告)号：US07697146B2
公开(公告)日：2010-04-13
申请号：US11362240
申请日：2006-02-24
申请人： Erwan Le Roy , Chun-Cheng Tsao , Theodore R. Lundquist
发明人： Erwan Le Roy , Chun-Cheng Tsao , Theodore R. Lundquist
IPC分类号： G01B11/02
CPC分类号： H01J37/3174 , B23K26/03 , B23K26/032 , B82Y10/00 , B82Y40/00
摘要： An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, light is directed on the integrated circuit and based upon the detection of interference fringes, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. When the floor approaches the underlying circuit structures, some light is reflected from the floor of the trench and some light penetrates the substrate and is reflected off the underlying circuit structures. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Processing may be controlled as function of the detection of interference fringes.
摘要翻译：一种使用光学干涉条纹处理集成电路的装置和方法。在处理期间，光被引导到集成电路上，并且基于干涉条纹的检测，可以控制进一步的处理。一种实施方案涉及集成电路的带电粒子束处理作为干涉条纹检测的功能。在集成电路的衬底中或其上执行带电粒子束沟槽铣削操作。光照在沟槽的地板上。当地板接近下面的电路结构时，一些光从沟槽的底部反射，并且一些光穿透衬底并从下面的电路结构反射。干涉条纹可以由从地板反射的光与来自电路结构的光之间的建构性或破坏性干扰形成。作为检测干涉条纹的功能，可以控制处理。

10. 发明授权

US06955930B2 Method for determining thickness of a semiconductor substrate at the floor of a trench 失效
标题翻译：确定沟槽底部的半导体衬底的厚度的方法
公开(公告)号：US06955930B2
公开(公告)日：2005-10-18
申请号：US10161272
申请日：2002-05-30
申请人： Erwan Le Roy , Chun-Cheng Tsao
发明人： Erwan Le Roy , Chun-Cheng Tsao
IPC分类号： H01J37/30 , H01J37/305 , H01L21/3065 , H01L21/66
CPC分类号： H01J37/3005 , H01J37/3056 , H01J2237/30466 , H01L21/3065
摘要： Apparatus and method for exposing a selected feature of an integrated circuit device such as a selected portion of the metallization layer, from the backside of the integrated circuit substrate without disturbing adjacent features of the device such as the active semiconductor regions. This is performed using an FIB (focused ion beam) etching process in conjunction with observation by an optical microscope to form a trench through the substrate. The process includes a precise optical endpointing technique to monitor the remaining thickness of the semiconductor substrate at the floor of the trench. It is important to terminate etching of the trench so that the trench floor extends as close to the active semiconductor structures as desired and yet is not detrimental to device operation. This is done without introducing a need for any additional tool. This is carried out using an infra-red optical technique which observes the interference fringes generated by the reflections from the silicon substrate surface and from semiconductor device circuitry layers to quantify the remaining semiconductor substrate thickness in the trench.
摘要翻译：用于从集成电路衬底的背面暴露诸如金属化层的选定部分的集成电路器件的选定特征的装置和方法，而不干扰诸如有源半导体区域的器件的相邻特征。这是通过FIB（聚焦离子束）蚀刻工艺结合光学显微镜的观察来进行的，以通过衬底形成沟槽。该方法包括精确的光学终点技术，以监测沟槽底部的半导体衬底的剩余厚度。重要的是终止沟槽的蚀刻，使得沟槽底板根据需要延伸到接近有源半导体结构，并且不会对器件操作产生不利影响。这不需要任何额外的工具就可以完成。这使用红外光学技术进行，该技术观察由硅衬底表面和半导体器件电路层的反射产生的干涉条纹，以量化沟槽中剩余的半导体衬底厚度。

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