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1. 发明授权

US06960836B2 Reinforced bond pad 有权
标题翻译：钢筋垫
公开(公告)号：US06960836B2
公开(公告)日：2005-11-01
申请号：US10675260
申请日：2003-09-30
申请人： Mark Adam Bachman , Daniel Patrick Chesire , Sailesh Mansinh Merchant , John William Osenbach , Kurt George Steiner
发明人： Mark Adam Bachman , Daniel Patrick Chesire , Sailesh Mansinh Merchant , John William Osenbach , Kurt George Steiner
IPC分类号： H01L21/60 , H01L23/00 , H01L23/485 , H01L23/52
CPC分类号： H01L24/05 , H01L21/768 , H01L23/562 , H01L24/03 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05082 , H01L2224/05093 , H01L2224/05558 , H01L2224/05567 , H01L2224/05624 , H01L2224/05647 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2224/05552
摘要： Disclosed herein is a reinforcing system and method for reinforcing a contact pad of an integrated circuit. Specifically exemplified is a system and method that comprises a reinforcing structure interposed between a top contact pad layer and an underlying metal layer.
摘要翻译：本文公开了一种用于加强集成电路的接触焊盘的增强系统和方法。具体示出的是包括插入在顶部接触垫层和下面的金属层之间的加强结构的系统和方法。

2. 发明授权

US6034405A Bonding of aluminum oxide components to silicons substrates 失效
标题翻译：氧化铝组分与硅衬底的接合
公开(公告)号：US6034405A
公开(公告)日：2000-03-07
申请号：US899291
申请日：1997-07-22
申请人： Michael Francis Brady , Mindaugas Fernand Dautartas , James F. Dormer , Sailesh Mansinh Merchant , Casimir Roman Nijander , John William Osenbach
发明人： Michael Francis Brady , Mindaugas Fernand Dautartas , James F. Dormer , Sailesh Mansinh Merchant , Casimir Roman Nijander , John William Osenbach
IPC分类号： G02B6/42 , H01L31/0232 , G02B6/32 , H01L31/00
CPC分类号： G02B6/4204 , G02B6/4236 , G02B6/4244 , G02B6/4257 , G02B6/4274
摘要： The invention is a method and resulting device which provides a strong bond between a silicon substrate and an oxide component mounted within a cavity in the substrate. A layer of titanium, for example, is deposited on the walls of the cavity, followed by deposition of a layer of aluminum. The structure is preferably annealed to form titanium silicide and titanium-aluminum interface layers. The component is then bonded to the aluminum layer.
摘要翻译：本发明是一种方法和产生的装置，其在硅衬底和安装在衬底中的空腔内的氧化物组件之间提供强结合。例如，一层钛沉积在空腔的壁上，随后沉积一层铝。该结构优选被退火以形成硅化钛和钛 - 铝界面层。然后将该组分结合到铝层。

3. 发明授权

US6119921A Bonding of aluminum oxide components to silicon substrates 有权
标题翻译：氧化铝组分与硅衬底的结合
公开(公告)号：US6119921A
公开(公告)日：2000-09-19
申请号：US252729
申请日：1999-02-19
申请人： Michael Francis Brady , Mindaugas Fernand Dautartas , James F. Dormer , Sailesh Mansinh Merchant , Casimir Roman Nijander , John William Osenbach
发明人： Michael Francis Brady , Mindaugas Fernand Dautartas , James F. Dormer , Sailesh Mansinh Merchant , Casimir Roman Nijander , John William Osenbach
IPC分类号： G02B6/42 , B23K31/00 , B23K101/40 , G02B13/18
CPC分类号： G02B6/4204 , G02B6/4236 , G02B6/4244 , G02B6/4257 , G02B6/4274
摘要： The invention is a method and resulting device which provides a strong bond between a silicon substrate and an oxide component mounted within a cavity in the substrate. A layer of titanium, for example, is deposited on the walls of the cavity, followed by deposition of a layer of aluminum. The structure is preferably annealed to form titanium silicide and titanium-aluminum interface layers. The component is then bonded to the aluminum layer.
摘要翻译：本发明是一种方法和产生的装置，其在硅衬底和安装在衬底中的空腔内的氧化物组件之间提供强结合。例如，一层钛沉积在空腔的壁上，随后沉积一层铝。该结构优选被退火以形成硅化钛和钛 - 铝界面层。然后将该组分结合到铝层。

4. 发明授权

US07724359B2 Method of making electronic entities 有权
标题翻译：制作电子实体的方法
公开(公告)号：US07724359B2
公开(公告)日：2010-05-25
申请号：US12154794
申请日：2008-05-27
申请人： Ahmed Nur Amin , Mark Adam Bachman , Frank A. Baiocchi , John Michael DeLucca , John William Osenbach
发明人： Ahmed Nur Amin , Mark Adam Bachman , Frank A. Baiocchi , John Michael DeLucca , John William Osenbach
IPC分类号： G01N21/00
CPC分类号： H01L22/12 , H01L21/4846 , H01L22/20 , H01L23/49866 , H01L24/13 , H01L2224/81444 , H01L2224/85444 , H01L2924/01013 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H05K3/244
摘要： Many electronic entities such as integrated circuits and discrete power devices have contact pads formed from successively deposited layers of nickel and a second metal such as gold. The resulting pad structure is used to make external electrical connection such as solder connection. Problems associated with failure of such connections are avoidable by inspecting the surface of the nickel layer for excessive small particle formation.
摘要翻译：诸如集成电路和分立功率器件的许多电子实体具有由连续沉积的镍层和诸如金的第二金属形成的接触焊盘。所得到的焊盘结构用于形成诸如焊接连接的外部电连接。通过检查镍层的表面以避免过度的小颗粒形成，可避免与这种连接的故障有关的问题。

5. 发明授权

US07671436B2 Electronic packages 有权
标题翻译：电子包装
公开(公告)号：US07671436B2
公开(公告)日：2010-03-02
申请号：US12151108
申请日：2008-05-02
申请人： Ahmed Nur Amin , Mark Adam Bachman , David Lee Crouthamel , John William Osenbach , Brian Thomas Vaccaro
发明人： Ahmed Nur Amin , Mark Adam Bachman , David Lee Crouthamel , John William Osenbach , Brian Thomas Vaccaro
IPC分类号： H01L31/00
CPC分类号： H05K1/0271 , H01L23/49811 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/05647 , H01L2224/1132 , H01L2224/11849 , H01L2224/13016 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/45144 , H01L2224/48624 , H01L2224/48647 , H01L2224/8121 , H01L2224/81815 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H05K3/3436 , H05K2201/0133 , H05K2201/10674 , H01L2924/00014 , H01L2924/01039 , H01L2224/13099 , H01L2924/00
摘要： Assemblies involving integrated circuit dies (e.g. packaged integrated circuits) and packaged dies electrically connected to circuit boards at times mechanically fail at conducting pads used for electrical interconnection. Such failure is mitigated by underlying appropriate pads with a compliant region having specific characteristics.
摘要翻译：涉及集成电路管芯（例如封装的集成电路）和与电路板电连接的封装模具的组件有时在用于电互连的导电焊盘处机械故障。这种故障由具有具有特定特征的柔顺区域的下层适当的垫减轻。

6. 发明申请

US20090298286A1 Method of making electronic entities 有权
标题翻译：制作电子实体的方法
公开(公告)号：US20090298286A1
公开(公告)日：2009-12-03
申请号：US12154794
申请日：2008-05-27
申请人： Ahmed Nur Amin , Mark Adam Bachman , Frank A. Baiocchi , John Michael DeLucca , John William Osenbach
发明人： Ahmed Nur Amin , Mark Adam Bachman , Frank A. Baiocchi , John Michael DeLucca , John William Osenbach
IPC分类号： H01L21/44
CPC分类号： H01L22/12 , H01L21/4846 , H01L22/20 , H01L23/49866 , H01L24/13 , H01L2224/81444 , H01L2224/85444 , H01L2924/01013 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H05K3/244
摘要： Many electronic entities such as integrated circuits and discrete power devices have contact pads formed from successively deposited layers of nickel and a second metal such as gold. The resulting pad structure is used to make external electrical connection such as solder connection. Problems associated with failure of such connections are avoidable by inspecting the surface of the nickel layer for excessive small particle formation.
摘要翻译：诸如集成电路和分立功率器件的许多电子实体具有由连续沉积的镍层和诸如金的第二金属形成的接触焊盘。所得到的焊盘结构用于形成诸如焊接连接的外部电连接。通过检查镍层的表面以避免过度的小颗粒形成，可避免与这种连接的故障有关的问题。

7. 发明申请

US20090273078A1 Electronic packages 有权
标题翻译：电子包装
公开(公告)号：US20090273078A1
公开(公告)日：2009-11-05
申请号：US12151108
申请日：2008-05-02
申请人： Ahmed Nur Amin , Mark Adam Bachman , David Lee Crouthamel , John William Osenbach , Brian Thomas Vaccaro
发明人： Ahmed Nur Amin , Mark Adam Bachman , David Lee Crouthamel , John William Osenbach , Brian Thomas Vaccaro
IPC分类号： H01L23/48 , H05K1/00
CPC分类号： H05K1/0271 , H01L23/49811 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/05647 , H01L2224/1132 , H01L2224/11849 , H01L2224/13016 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/45144 , H01L2224/48624 , H01L2224/48647 , H01L2224/8121 , H01L2224/81815 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H05K3/3436 , H05K2201/0133 , H05K2201/10674 , H01L2924/00014 , H01L2924/01039 , H01L2224/13099 , H01L2924/00
摘要： Assemblies involving integrated circuit dies (e.g. packaged integrated circuits) and packaged dies electrically connected to circuit boards at times mechanically fail at conducting pads used for electrical interconnection. Such failure is mitigated by underlying appropriate pads with a compliant region having specific characteristics.
摘要翻译：涉及集成电路管芯（例如封装的集成电路）和与电路板电连接的封装模具的组件有时在用于电互连的导电焊盘处机械故障。这种故障由具有具有特定特征的柔顺区域的下层适当的垫减轻。

8. 发明授权

US07541669B2 Semiconductor device package with base features to reduce leakage 有权
标题翻译：半导体器件封装具有基极特性，可减少泄漏
公开(公告)号：US07541669B2
公开(公告)日：2009-06-02
申请号：US11788346
申请日：2007-04-19
申请人： Patrick Joseph Carberry , Jeffery John Gilbert , George John Libricz, Jr. , Ralph Salvatore Moyer , John William Osenbach , Hugo Fernando Safar , Thomas Herbert Shilling
发明人： Patrick Joseph Carberry , Jeffery John Gilbert , George John Libricz, Jr. , Ralph Salvatore Moyer , John William Osenbach , Hugo Fernando Safar , Thomas Herbert Shilling
IPC分类号： H01L33/00 , H01L23/495 , H01L23/28 , H01L23/34
CPC分类号： H01L23/49548 , H01L23/4334 , H01L23/49541 , H01L23/49861 , H01L24/48 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014 , H01L2924/01322 , H01L2924/13091 , H01L2924/14 , H01L2924/16195 , H01L2924/19041 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewall interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.
摘要翻译：半导体器件封装包括包括基底和侧壁的容器。基座被配置为支撑半导体器件芯片，并且引线框架延伸穿过至少一个侧壁。引导框架在侧壁内的一部分具有穿透引线框架的至少一个孔。侧壁材料延伸到孔中，从而形成强界面结合，其提供低泄漏侧壁引线框架界面。底座具有位于至少一个侧壁的厚度内并与至少一个侧壁接合的折入特征，从而形成低泄漏的底壁 - 侧壁界面。基座的顶表面具有凹槽，该凹槽位于至少一个侧壁的厚度内并与至少一个侧壁接合，由此增强了低泄漏的底壁 - 侧壁界面。

9. 发明授权

US07368326B2 Methods and apparatus to reduce growth formations on plated conductive leads 有权
标题翻译：减少电镀导电引线上生长结构的方法和装置
公开(公告)号：US07368326B2
公开(公告)日：2008-05-06
申请号：US10855148
申请日：2004-05-27
申请人： John William Osenbach , Brian Dale Potteiger , Richard Lawrence Shook , Brian Thomas Vaccaro
发明人： John William Osenbach , Brian Dale Potteiger , Richard Lawrence Shook , Brian Thomas Vaccaro
IPC分类号： H01L21/50 , H01L21/48 , H01L21/44 , H01L23/495 , H01L23/52 , H01L23/48 , H01L23/40
CPC分类号： H01L21/4821 , H01L23/49582 , H01L24/48 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A process includes annealing one or more plated conductive leads at a predetermined temperature. The one or more plated conductive leads are plated with one or more layers, where each layer comprises a material. The predetermined temperature is greater than or equal to approximately a melting point of one of the materials. The annealing can reduce growth formations, such as whiskers, on the one or more conductive leads. Lead frames and other devices having plated conductive leads may be subjected to the process, and the resultant plated conductive leads will have fewer growth formations than plated conductive leads not subjected to the process. The plated conductive leads may be trimmed and formed prior to or after the anneal.
摘要翻译：一种方法包括在预定温度下退火一个或多个镀覆的导电引线。一个或多个镀覆的导电引线镀有一层或多层，其中每层包括材料。预定温度大于或等于其中一种材料的大约熔点。退火可以减少一个或多个导电引线上的生长结构，例如晶须。可以对具有镀覆导电引线的引线框架和其他器件进行处理，并且所生成的镀覆导电引线将比不经过该工艺的镀覆导电引线具有更少的生长结构。镀层的导电引线可以在退火之前或之后进行修整和形成。

10. 发明授权

US06862378B2 Silicon-based high speed optical wiring board 有权
标题翻译：硅基高速光布线板
公开(公告)号：US06862378B2
公开(公告)日：2005-03-01
申请号：US10279408
申请日：2002-10-24
申请人： Mark Karnacewicz , John William Osenbach , Alexandru Paunescu
发明人： Mark Karnacewicz , John William Osenbach , Alexandru Paunescu
IPC分类号： G02B6/42 , G02B6/26
CPC分类号： G02B6/4204 , G02B6/4201
摘要： An optical wire board which utilizes a silicon substrate as the base for both the optical subassembly and the electrical RF transmitting circuit. An optical fiber is preferably passively aligned to the active optical device mounted on the optical subassembly using a V-groove etched into the silicon (and may include a lens or other optical element positioned between the fiber and the active device). An integrated circuit for coupling the active optical device to external contacts is preferably flip-chip mounted to the silicon substrate upon pads disposed on precisely defined edges around a cavity etched beneath the circuit, the inclusion of the cavity beneath the electrical circuit functioning to minimize the dielectric loading effect of the silicon substrate on the integrated circuit.
摘要翻译：一种利用硅衬底作为光学子组件和RF射频发射电路的基底的光线板。光纤优选被动地与安装在光学子组件上的有源光学器件对准，使用蚀刻到硅中的V沟槽（并且可以包括位于光纤和有源器件之间的透镜或其它光学元件）。用于将有源光学器件耦合到外部触点的集成电路优选地被倒装芯片安装到硅衬底上，所述焊盘设置在蚀刻在电路下面的空腔周围的精确限定的边缘上，包括在电路下面的空腔，硅衬底对集成电路的介电负载效应。

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