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1. 发明授权

US07715410B2 Queueing system for processors in packet routing operations 有权
标题翻译：分组路由操作中处理器的排队系统
公开(公告)号：US07715410B2
公开(公告)日：2010-05-11
申请号：US11277293
申请日：2006-03-23
申请人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
发明人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
IPC分类号： H04L12/56 , G06F13/00 , G06F12/00
CPC分类号： G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： In a data-packet processor, a configurable queuing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeuing of the selected packet identifiers.
摘要翻译：在数据包处理器中，用于处理期间的分组计费的可配置排队系统具有排列在一个或多个集群中的多个队列，用于创建用于到达分组的分组标识符的识别机制，用于将分组标识符插入到队列中的插入逻辑确定插入分组标识符到哪个队列，以及用于从队列中选择分组标识符以启动所识别的分组的处理，完成的分组的下载或用于重新选择所选择的分组标识符的选择逻辑。

2. 发明授权

US07551626B2 Queueing system for processors in packet routing operations 有权
标题翻译：分组路由操作中处理器的排队系统
公开(公告)号：US07551626B2
公开(公告)日：2009-06-23
申请号：US11360338
申请日：2006-02-23
申请人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
发明人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
IPC分类号： H04L12/56 , G06F3/00 , G06F13/00
CPC分类号： G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.
摘要翻译：在数据包处理器中，用于处理期间的分组计费的可配置排队系统具有排列在一个或多个集群中的多个队列，用于创建用于到达分组的分组标识符的识别机制，用于将分组标识符插入到队列中的插入逻辑确定插入分组标识符到哪个队列，以及用于从队列中选择分组标识符以启动已识别分组的处理，完成的分组的下载或用于重新选择所选分组标识符的选择逻辑。

3. 发明申请

US20060159104A1 QUEUEING SYSTEM FOR PROCESSORS IN PACKET ROUTING OPERATIONS 有权
标题翻译：分组路由操作中处理器的队列系统
公开(公告)号：US20060159104A1
公开(公告)日：2006-07-20
申请号：US11277293
申请日：2006-03-23
申请人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
发明人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
IPC分类号： H04L12/56
CPC分类号： G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.
摘要翻译：在数据包处理器中，在处理期间用于分组计费的可配置排队系统具有排列在一个或多个集群中的多个队列，用于创建用于到达分组的分组标识符的识别机制，用于将分组标识符插入到队列中的插入逻辑确定插入分组标识符到哪个队列，以及用于从队列中选择分组标识符以启动已识别分组的处理，完成的分组的下载或用于重新选择所选分组标识符的选择逻辑。

4. 发明申请

US20060153197A1 Queueing system for processors in packet routing operations 有权
公开(公告)号：US20060153197A1
公开(公告)日：2006-07-13
申请号：US11360338
申请日：2006-02-23
申请人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
发明人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.

5. 发明授权

US07058064B2 Queueing system for processors in packet routing operations 有权
公开(公告)号：US07058064B2
公开(公告)日：2006-06-06
申请号：US09737375
申请日：2000-12-14
申请人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
发明人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
IPC分类号： H04L12/56 , G06F13/00 , G06F12/00
CPC分类号： G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.

6. 发明授权

US07032226B1 Methods and apparatus for managing a buffer of events in the background 有权
标题翻译：用于管理后台事件缓冲区的方法和装置
公开(公告)号：US07032226B1
公开(公告)日：2006-04-18
申请号：US09608750
申请日：2000-06-30
申请人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
发明人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
IPC分类号： G06F9/46
CPC分类号： G06F9/542 , G06F13/126 , G06F2209/544 , G06F2209/546
摘要： A background event buffer manager (BEBM) for ordering and accounting for events in a data processing system having a processor includes a port for receiving event identifications (IDs) from a device, a queuing function enabled for queuing event IDs received, and a notification function for notifying the processor of queued event IDs. The BEBM handles all event ordering and accounting for the processor. The BEBM in preferred embodiments queues events by type with priority and by priority within type, and also handles sending acknowledgement to the device when processing on each event is concluded, and buffers the acknowledgement process. In particular embodiments the apparatus and method is taught as a packet processing router engine.
摘要翻译：用于对具有处理器的数据处理系统中的事件进行排序和计费的后台事件缓冲器管理器（BEBM）包括用于从设备接收事件标识（ID）的端口，用于排队接收的事件ID的排队功能和通知功能用于通知处理器排队的事件ID。 BEBM处理处理器的所有事件排序和计费。优选实施例中的BEBM按照类型优先级和类型下的优先级排队事件，并且还处理在对每个事件的处理结束时向设备发送确认，并且缓冲确认过程。在特定实施例中，该装置和方法被教导为分组处理路由器引擎。

7. 发明授权

US07502876B1 Background memory manager that determines if data structures fits in memory with memory state transactions map 有权
标题翻译：后台存储器管理器，用于确定数据结构是否与存储器状态事务映射相匹配
公开(公告)号：US07502876B1
公开(公告)日：2009-03-10
申请号：US09602279
申请日：2000-06-23
申请人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
发明人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
IPC分类号： G06F13/00 , G06F12/08 , G06F12/00
CPC分类号： G06F12/023 , G06F13/28
摘要： A background memory manager (BMM) for managing a memory in a data processing system has circuitry for transferring data to and from an outside device and to and from a memory, a memory state map associated with the memory, and a communication link to a processor. The BMM manages the memory, determining if each data structure fits into the memory, deciding exactly where to place the data structure in memory, performing all data transfers between the outside device and the memory, and maintaining the memory state map according to memory transactions made, and informing the processor of new data and its location. In preferred embodiments the BMM, in the process of storing data structures into the memory, provides an identifier for each structure to the processor. The system is particularly applicable to Internet packet processing in packet routers.
摘要翻译：用于管理数据处理系统中的存储器的后台存储器管理器（BMM）具有用于向外部设备传送数据和从外部设备传送数据到存储器和从存储器传送数据的存储器的电路，与存储器相关联的存储器状态映射以及到处理器的通信链路。 BMM管理存储器，确定每个数据结构是否适合存储器，准确地确定数据结构放置在存储器中的位置，在外部设备和存储器之间执行所有数据传输，并根据存储器事务来保持存储器状态映射并通知处理器新数据及其位置。在优选实施例中，BMM在将数据结构存储到存储器中的过程中向处理器提供每个结构的标识符。该系统特别适用于分组路由器中的因特网分组处理。

8. 发明申请

US20060225080A1 METHODS AND APPARATUS FOR MANAGING A BUFFER OF EVENTS IN THE BACKGROUND 有权
标题翻译：在背景下管理事件缓冲的方法和装置
公开(公告)号：US20060225080A1
公开(公告)日：2006-10-05
申请号：US11278747
申请日：2006-04-05
申请人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
发明人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
IPC分类号： G06F9/46
CPC分类号： G06F9/542 , G06F13/126 , G06F2209/544 , G06F2209/546
摘要： A background event buffer manager (BEBM) for ordering and accounting for events in a data processing system having a processor includes a port for receiving event identifications (IDs) from a device, a queuing function enabled for queuing event IDs received, and a notification function for notifying the processor of queued event IDs. The BEBM handles all event ordering and accounting for the processor. The BEBM in preferred embodiments queues events by type with priority and by priority within type, and also handles sending acknowledgement to the device when processing on each event is concluded, and buffers the acknowledgement process. In particular embodiments the apparatus and method is taught as a packet processing router engine.
摘要翻译：用于对具有处理器的数据处理系统中的事件进行排序和计费的后台事件缓冲器管理器（BEBM）包括用于从设备接收事件标识（ID）的端口，用于排队接收的事件ID的排队功能和通知功能用于通知处理器排队的事件ID。 BEBM处理处理器的所有事件排序和计费。优选实施例中的BEBM按照类型优先级和类型下的优先级排队事件，并且还处理在对每个事件的处理结束时向设备发送确认，并且缓冲确认过程。在特定实施例中，该装置和方法被教导为分组处理路由器引擎。

9. 发明授权

US07661112B2 Methods and apparatus for managing a buffer of events in the background 有权
标题翻译：用于管理后台事件缓冲区的方法和装置
公开(公告)号：US07661112B2
公开(公告)日：2010-02-09
申请号：US11278747
申请日：2006-04-05
申请人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
发明人： Mario Nemirovsky , Narendra Sankar , Adolfo Nemirovsky , Enric Musoll
IPC分类号： G06F9/46 , G06F12/00
CPC分类号： G06F9/542 , G06F13/126 , G06F2209/544 , G06F2209/546
摘要： A background event buffer manager (BEBM) for ordering and accounting for events in a data processing system having a processor includes a port for receiving event identifications (IDs) from a device, a queuing function enabled for queuing event IDs received, and a notification function for notifying the processor of queued event IDs. The BEBM handles all event ordering and accounting for the processor. The BEBM in preferred embodiments queues events by type with priority and by priority within type, and also handles sending acknowledgement to the device when processing on each event is concluded, and buffers the acknowledgement process. In particular embodiments the apparatus and method is taught as a packet processing router engine.
摘要翻译：用于对具有处理器的数据处理系统中的事件进行排序和计费的后台事件缓冲器管理器（BEBM）包括用于从设备接收事件标识（ID）的端口，用于排队接收的事件ID的排队功能和通知功能用于通知处理器排队的事件ID。 BEBM处理处理器的所有事件排序和计费。优选实施例中的BEBM按照类型优先级和类型下的优先级排队事件，并且还处理在对每个事件的处理结束时向设备发送确认，并且缓冲确认过程。在特定实施例中，该装置和方法被教导为分组处理路由器引擎。

10. 发明申请

US20070143580A1 METHODS AND APPARATUS FOR IMPROVING FETCHING AND DISPATCH OF INSTRUCTIONS IN MULTITHREADED PROCESSORS 有权
标题翻译：用于改进多处理器处理器中的指令和指示的方法和装置
公开(公告)号：US20070143580A1
公开(公告)日：2007-06-21
申请号：US11278874
申请日：2006-04-06
申请人： Enric Musoll , Mario Nemirovsky
发明人： Enric Musoll , Mario Nemirovsky
IPC分类号： G06F9/40
CPC分类号： G06F9/383 , G06F9/3804 , G06F9/3844 , G06F9/3851
摘要： In a multi-streaming processor, a system for fetching instructions from individual ones of multiple streams to an instruction pipeline is provided, comprising a fetch algorithm for selecting from which stream to fetch an instruction, and one or more predictors for forecasting whether a load instruction will hit or miss the cache or a branch will be taken. The prediction or predictions are used by the fetch algorithm in determining from which stream to fetch. In some cases probabilities are determined and also used in decisions, and predictors may be used at either or both of fetch and dispatch stages.
摘要翻译：在多流处理器中，提供用于从多个流中的各个流到指令流水线获取指令的系统，包括用于从哪个流中取出指令的提取算法，以及用于预测加载指令的一个或多个预测器将击中或错过缓存或分支将被采取。提取算法使用预测或预测来确定从哪个流获取。在某些情况下，确定概率并且也用于决策，并且预测器可以在获取和调度阶段中的任一个或两者使用。

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