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1. 发明申请

US20080224204A1 PROCESS FOR MANUFACTURING A MULTI-DRAIN ELECTRONIC POWER DEVICE INTEGRATED IN SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICE 有权
标题翻译：用于制造集成在半导体衬底和相应器件中的多电子电力器件的制造方法
公开(公告)号：US20080224204A1
公开(公告)日：2008-09-18
申请号：US11971163
申请日：2008-01-08
申请人： Mario Giuseppe Saggio , Ferruccio Frisina , Simone Rascuna
发明人： Mario Giuseppe Saggio , Ferruccio Frisina , Simone Rascuna
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/66712
摘要： A process manufactures a multi-drain power electronic device integrated on a semiconductor substrate of a first type of conductivity whereon a drain semiconductor layer is formed. The process includes: forming a first semiconductor epitaxial layer of the first type of conductivity of a first value of resistivity forming the drain epitaxial layer on the semiconductor substrate, forming first sub-regions of a second type of conductivity by means of a first selective implant step with a first implant dose, forming second sub-regions of the first type of conductivity by means of a second implant step with a second implant dose, forming a surface semiconductor layer wherein body regions of the second type of conductivity are formed being aligned with the first sub-regions, carrying out a thermal diffusion process so that the first sub-regions form a single electrically continuous column region being aligned and in electric contact with the body regions.
摘要翻译：一种工艺制造集成在第一导电类型的半导体衬底上的多漏功率电子器件，其中形成漏极半导体层。该方法包括：在半导体衬底上形成第一类电导率的第一半导体外延层，其形成第一导电类型的第一电阻率，形成第二类型的导电性的第一子区域，借助于第一选择性注入以第一注入剂量进行步骤，借助于具有第二注入剂量的第二注入步骤形成第一类型导电性的第二子区域，形成表面半导体层，其中形成第二导电类型的主体区域与所述第一子区域进行热扩散处理，使得所述第一子区域形成与所述身体区域对准并电接触的单个电连续列区域。

2. 发明申请

US20110034010A1 PROCESS FOR MANUFACTURING A MULTI-DRAIN ELECTRONIC POWER DEVICE INTEGRATED IN SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICE 审中-公开
标题翻译：用于制造集成在半导体衬底和相应器件中的多电子电力器件的制造方法
公开(公告)号：US20110034010A1
公开(公告)日：2011-02-10
申请号：US12905623
申请日：2010-10-15
申请人： Mario Giuseppe Saggio , Ferruccio Frisina , Simone Rascuna
发明人： Mario Giuseppe Saggio , Ferruccio Frisina , Simone Rascuna
IPC分类号： H01L21/20
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0886 , H01L29/1095 , H01L29/66712
摘要： A process manufactures a multi-drain power electronic device on a semiconductor substrate of a first conductivity type and includes: forming a first semiconductor layer of the first conductivity type on the substrate, forming a second semiconductor layer of a second conductivity type on the first semiconductor layer, forming, in the second semiconductor layer, a first plurality of implanted regions of the first conductivity type using a first implant dose, forming, above the second semiconductor layer, a superficial semiconductor layer of the first conductivity type, forming in the surface semiconductor layer body regions of the second conductivity type, thermally diffusing the implanted regions to form a plurality of electrically continuous implanted column regions along the second semiconductor layer, the plurality of implanted column regions delimiting a plurality of column regions of the second conductivity type aligned with the body regions.
摘要翻译：一种工艺在第一导电类型的半导体衬底上制造多漏电功率电子器件，包括：在衬底上形成第一导电类型的第一半导体层，在第一半导体上形成第二导电类型的第二半导体层在所述第二半导体层中，使用第一注入剂量在所述第二半导体层中形成所述第一导电类型的第一多个注入区域，在所述第二半导体层上形成所述第一导电类型的表面半导体层，在所述表面半导体中形成第二导电类型的层体区域，热扩散注入区域以沿着第二半导体层形成多个电连续注入的列区域，多个注入的列区域限定具有与第二导电类型对准的多个第二导电类型的列区域身体区域。

3. 发明授权

US08012832B2 Process for manufacturing a multi-drain electronic power device integrated in semiconductor substrate and corresponding device 有权
标题翻译：用于制造集成在半导体衬底中的多排放电子功率器件和相应器件的工艺
公开(公告)号：US08012832B2
公开(公告)日：2011-09-06
申请号：US11971163
申请日：2008-01-08
申请人： Mario Giuseppe Saggio , Ferruccio Frisina , Simone Rascuna
发明人： Mario Giuseppe Saggio , Ferruccio Frisina , Simone Rascuna
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/66712
摘要： A process manufactures a multi-drain power electronic device integrated on a semiconductor substrate of a first type of conductivity whereon a drain semiconductor layer is formed. The process includes: forming a first semiconductor epitaxial layer of the first type of conductivity of a first value of resistivity forming the drain epitaxial layer on the semiconductor substrate, forming first sub-regions of a second type of conductivity by a first selective implant step with a first implant dose, forming second sub-regions of the first type of conductivity by a second implant step with a second implant dose, and forming a surface semiconductor layer. The process also includes forming body regions of the second type of conductivity aligned with the first sub-regions, and carrying out a thermal diffusion process so that the first sub-regions form a single electrically continuous column region aligned and in electric contact with the body regions.
摘要翻译：一种工艺制造集成在第一导电类型的半导体衬底上的多漏功率电子器件，其中形成漏极半导体层。该方法包括：在半导体衬底上形成形成第一导电类型的第一电阻值的第一类电导率的第一半导体外延层，通过第一选择性注入步骤形成具有第二类导电性的第一子区，第一植入剂量，通过具有第二注入剂量的第二注入步骤形成第一类型导电性的第二子区域，以及形成表面半导体层。该方法还包括形成与第一子区域对准的第二类型的导电体的体区，并且进行热扩散处理，使得第一子区域形成对准并与身体电接触的单个电连续的列区域地区。

4. 发明授权

US07838927B2 Process for manufacturing a multi-drain electronic power device integrated in semiconductor substrate and corresponding device 有权
标题翻译：用于制造集成在半导体衬底中的多排放电子功率器件和相应器件的工艺
公开(公告)号：US07838927B2
公开(公告)日：2010-11-23
申请号：US11971168
申请日：2008-01-08
申请人： Mario Giuseppe Saggio , Ferruccio Frisina , Simone Rascuna
发明人： Mario Giuseppe Saggio , Ferruccio Frisina , Simone Rascuna
IPC分类号： H01L27/108
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0886 , H01L29/1095 , H01L29/66712
摘要： A process manufactures a multi-drain power electronic device on a semiconductor substrate of a first conductivity type and includes: forming a first semiconductor layer of the first conductivity type on the substrate, forming a second semiconductor layer of a second conductivity type on the first semiconductor layer, forming, in the second semiconductor layer, a first plurality of implanted regions of the first conductivity type using a first implant dose, forming, above the second semiconductor layer, a superficial semiconductor layer of the first conductivity type, forming in the surface semiconductor layer body regions of the second conductivity type, thermally diffusing the implanted regions to form a plurality of electrically continuous implanted column regions along the second semiconductor layer, the plurality of implanted column regions delimiting a plurality of column regions of the second conductivity type aligned with the body regions.
摘要翻译：一种工艺在第一导电类型的半导体衬底上制造多漏电功率电子器件，包括：在衬底上形成第一导电类型的第一半导体层，在第一半导体上形成第二导电类型的第二半导体层在所述第二半导体层中，使用第一注入剂量在所述第二半导体层中形成所述第一导电类型的第一多个注入区域，在所述第二半导体层上形成所述第一导电类型的表面半导体层，在所述表面半导体中形成第二导电类型的层体区域，热扩散注入区域以沿着第二半导体层形成多个电连续注入的列区域，多个注入的列区域限定具有与第二导电类型对准的多个第二导电类型的列区域身体区域。

5. 发明申请

US20090001460A1 PROCESS FOR MANUFACTURING A MULTI-DRAIN ELECTRONIC POWER DEVICE INTEGRATED IN SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICE 有权
标题翻译：用于制造集成在半导体衬底和相应器件中的多电子电力器件的制造方法
公开(公告)号：US20090001460A1
公开(公告)日：2009-01-01
申请号：US11971168
申请日：2008-01-08
申请人： Mario Giuseppe Saggio , Ferruccio Frisina , Simone Rascuna
发明人： Mario Giuseppe Saggio , Ferruccio Frisina , Simone Rascuna
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0886 , H01L29/1095 , H01L29/66712
摘要： A process manufactures a multi-drain power electronic device on a semiconductor substrate of a first conductivity type and includes: forming a first semiconductor layer of the first conductivity type on the substrate, forming a second semiconductor layer of a second conductivity type on the first semiconductor layer, forming, in the second semiconductor layer, a first plurality of implanted regions of the first conductivity type using a first implant dose, forming, above the second semiconductor layer, a superficial semiconductor layer of the first conductivity type, forming in the surface semiconductor layer body regions of the second conductivity type, thermally diffusing the implanted regions to form a plurality of electrically continuous implanted column regions along the second semiconductor layer, the plurality of implanted column regions delimiting a plurality of column regions of the second conductivity type aligned with the body regions.
摘要翻译：一种工艺在第一导电类型的半导体衬底上制造多漏电功率电子器件，包括：在衬底上形成第一导电类型的第一半导体层，在第一半导体上形成第二导电类型的第二半导体层在所述第二半导体层中，使用第一注入剂量在所述第二半导体层中形成所述第一导电类型的第一多个注入区域，在所述第二半导体层上形成所述第一导电类型的表面半导体层，在所述表面半导体中形成第二导电类型的层体区域，热扩散注入区域以沿着第二半导体层形成多个电连续注入的列区域，多个注入的列区域限定具有与第二导电类型对准的多个第二导电类型的列区域身体区域。

6. 发明授权

US08901652B2 Power MOSFET comprising a plurality of columnar structures defining the charge balancing region 有权
标题翻译：功率MOSFET包括限定电荷平衡区域的多个柱状结构
公开(公告)号：US08901652B2
公开(公告)日：2014-12-02
申请号：US12862976
申请日：2010-08-25
申请人： Mario Giuseppe Saggio , Alfio Guarnera , Simone Rascuna′
发明人： Mario Giuseppe Saggio , Alfio Guarnera , Simone Rascuna′
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/0878 , H01L29/42368 , H01L29/7811
摘要： An embodiment of a semiconductor structure for a power device integrated on a semiconductor substrate, of a first type of conductivity, and comprising:—an epitaxial layer, of said first type of conductivity, made on said semiconductor substrate, and having a plurality of column structures, of a second type of conductivity, to define a charge balancing region;—an active surface layer made on said epitaxial layer for housing a plurality of active regions; said epitaxial layer comprising a semiconductor separating layer arranged between the charge balancing region and the active surface layer, said semiconductor separating layer decoupling said column structures from said active regions.
摘要翻译：一种用于集成在半导体衬底上的第一类导电性的功率器件的半导体结构的实施例，包括： - 在所述半导体衬底上形成所述第一导电类型的外延层，并且具有多个柱结构，第二类型的导电性，以限定电荷平衡区域; - 在所述外延层上形成的用于容纳多个有源区域的有源表面层; 所述外延层包括布置在电荷平衡区域和有源表面层之间的半导体分离层，所述半导体分离层将所述柱结构与所述有源区域分离。

7. 发明授权

US08039898B2 Process for manufacturing a charge-balance power diode and an edge-termination structure for a charge-balance semiconductor power device 有权
标题翻译：用于制造电荷平衡功率二极管的工艺和用于电荷平衡半导体功率器件的边缘终端结构
公开(公告)号：US08039898B2
公开(公告)日：2011-10-18
申请号：US11824169
申请日：2007-06-28
申请人： Mario Giuseppe Saggio , Domenico Murabito , Ferruccio Frisina
发明人： Mario Giuseppe Saggio , Domenico Murabito , Ferruccio Frisina
IPC分类号： H01L29/66
CPC分类号： H01L29/7811 , H01L21/324 , H01L29/0615 , H01L29/0634 , H01L29/0661 , H01L29/0692 , H01L29/0847 , H01L29/41766 , H01L29/66128 , H01L29/66727 , H01L29/66734 , H01L29/73 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/8611 , H01L29/872
摘要： An embodiment of a process for manufacturing a semiconductor power device envisages the steps of: providing a body made of semiconductor material having a first top surface; forming an active region with a first type of conductivity in the proximity of the first top surface and inside an active portion of the body; and forming an edge-termination structure. The edge-termination structure is formed by: a ring region having the first type of conductivity and a first doping level, set within a peripheral edge portion of the body and electrically coupled to the active region; and a guard region, having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface and connecting the active region to the ring region. The process further envisages the steps of: forming a surface layer having the first type of conductivity on the first top surface, also at the peripheral edge portion, in contact with the guard region; and etching the surface layer in order to remove it above the edge portion in such a manner that the etch terminates inside the guard region.
摘要翻译：制造半导体功率器件的方法的一个实施例设想了以下步骤：提供由具有第一顶表面的半导体材料制成的本体; 在所述第一顶表面附近和所述主体的活动部分内部形成具有第一类型导电性的有源区; 并形成边缘终端结构。边缘终端结构由以下部分形成：具有第一类型的导电性和第一掺杂水平的环形区域，其设置在主体的外围边缘部分内并电耦合到有源区域; 以及保护区，其具有高于第一掺杂级的第一类型的导电性和第二掺杂级，设置在第一顶表面附近并将有源区连接到环区。该方法进一步设想了以下步骤：在第一顶表面上形成具有第一类型导电性的表面层，也在周边边缘部分形成与保护区域接触的表面层; 并且蚀刻表面层以便以这样的方式将其去除边缘部分，使得蚀刻终止于保护区域内。

8. 发明授权

US07871880B2 Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices 有权
标题翻译：用于制造集成在半导体衬底中的电子器件和相应器件的方法
公开(公告)号：US07871880B2
公开(公告)日：2011-01-18
申请号：US11971155
申请日：2008-01-08
申请人： Ferruccio Frisina , Mario Giuseppe Saggio
发明人： Ferruccio Frisina , Mario Giuseppe Saggio
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/44 , H01L21/28
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1608 , H01L29/42368 , H01L29/66068
摘要： A method manufactures a vertical power MOS transistor on a semiconductor substrate comprising a first superficial semiconductor layer of a first conductivity type, comprising: forming trench regions in the first semiconductor layer, filling in said trench regions with a second semiconductor layer of a second conductivity type, to form semiconductor portions of the second conductivity type contained in the first semiconductor layer, carrying out an ion implantation of a first dopant type in the semiconductor portions for forming respective implanted body regions of said second conductivity type, carrying out an ion implantation of a second dopant type in one of the implanted body regions for forming an implanted source region of the first conductivity type inside one of the body regions, carrying out an activation thermal process of the first and second dopant types with low thermal budget suitable to complete said formation of the body and source regions.
摘要翻译：一种制造半导体衬底上的垂直功率MOS晶体管的方法，包括：第一导电类型的第一表面半导体层，包括：在第一半导体层中形成沟槽区，用第二导电类型的第二半导体层填充所述沟槽区，以形成包含在第一半导体层中的第二导电类型的半导体部分，在用于形成所述第二导电类型的各个植入体区域的半导体部分中执行第一掺杂剂类型的离子注入，进行离子注入一个植入体区域中的第二掺杂剂类型，用于在一个体区内形成第一导电类型的注入源区域，进行适于完成所述形成的具有低热预算的第一和第二掺杂剂类型的活化热处理的身体和来源地区。

9. 发明申请

US20090159969A1 PROCESS FOR MANUFACTURING A SEMICONDUCTOR POWER DEVICE COMPRISING CHARGE-BALANCE COLUMN STRUCTURES AND RESPECTIVE DEVICE 有权
标题翻译：制造包含充电平衡柱结构和相关器件的半导体电源装置的方法
公开(公告)号：US20090159969A1
公开(公告)日：2009-06-25
申请号：US12296921
申请日：2006-04-11
申请人： Simona Lorenti , Cateno Marco Camalleri , Mario Giuseppe Saggio , Ferruccio Frisina
发明人： Simona Lorenti , Cateno Marco Camalleri , Mario Giuseppe Saggio , Ferruccio Frisina
IPC分类号： H01L27/088 , H01L21/20 , H01L21/336 , H01L29/78
CPC分类号： H01L21/3247 , H01L21/02057 , H01L21/02381 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L21/3065 , H01L21/324 , H01L27/088 , H01L29/045 , H01L29/0634 , H01L29/1095 , H01L29/66333 , H01L29/66712 , H01L29/73 , H01L29/7395 , H01L29/7802 , H01L29/8611 , H01L29/872
摘要： Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.
摘要翻译：一种制造半导体功率器件的方法，其中在具有第一导电类型的半导体本体中形成沟槽; 沟槽退火成型目的; 并通过外延生长填充半导体材料，以获得具有第二导电类型的第一列。外延生长通过在卤化物气体的存在下供给包含硅和含有第二导电类型的掺杂剂离子的气体进行，并且以掺杂剂离子的均匀分布发生。含气体掺杂剂离子的流动在外延生长期间根据线性斜坡而变化; 特别是在硬掩模存在下选择性地生长半导体材料的情况下，流量减少; 在非选择性生长的情况下，在没有硬掩模的情况下，流动增加。

10. 发明申请

US20080185594A1 METHOD FOR MANUFACTURING ELECTRONIC DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICES 有权
标题翻译：用于制造集成在半导体衬底和相应器件中的电子器件的方法
公开(公告)号：US20080185594A1
公开(公告)日：2008-08-07
申请号：US11971155
申请日：2008-01-08
申请人： Ferruccio Frisina , Mario Giuseppe Saggio
发明人： Ferruccio Frisina , Mario Giuseppe Saggio
IPC分类号： H01L29/24 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1608 , H01L29/42368 , H01L29/66068
摘要： A method manufactures a vertical power MOS transistor on a semiconductor substrate comprising a first superficial semiconductor layer of a first conductivity type, comprising: forming trench regions in the first semiconductor layer, filling in said trench regions with a second semiconductor layer of a second conductivity type, to form semiconductor portions of the second conductivity type contained in the first semiconductor layer, carrying out an ion implantation of a first dopant type in the semiconductor portions for forming respective implanted body regions of said second conductivity type, carrying out an ion implantation of a second dopant type in one of the implanted body regions for forming an implanted source region of the first conductivity type inside one of the body regions, carrying out an activation thermal process of the first and second dopant types with low thermal budget suitable to complete said formation of the body and source regions.
摘要翻译：一种制造半导体衬底上的垂直功率MOS晶体管的方法，包括：第一导电类型的第一表面半导体层，包括：在第一半导体层中形成沟槽区，用第二导电类型的第二半导体层填充所述沟槽区，以形成包含在第一半导体层中的第二导电类型的半导体部分，在用于形成所述第二导电类型的各个植入体区域的半导体部分中执行第一掺杂剂类型的离子注入，进行离子注入一个植入体区域中的第二掺杂剂类型，用于在一个体区内形成第一导电类型的注入源区域，进行适于完成所述形成的具有低热预算的第一和第二掺杂剂类型的活化热处理的身体和来源地区。

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