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1. 发明申请

US20060020743A1 Multi-queue address generator for start and end addresses in a multi-queue first-in first-out memory system 有权
标题翻译：多队列地址生成器，用于多队列先进先出内存系统中的起始和结束地址
公开(公告)号：US20060020743A1
公开(公告)日：2006-01-26
申请号：US11040926
申请日：2005-01-21
申请人： Mario Au , Jason Mo , Xiaoping Fang
发明人： Mario Au , Jason Mo , Xiaoping Fang
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F5/065
摘要： A multi-queue FIFO memory device that uses existing pins of the device to load a desired number of queues (N) into a queue number register is provided. The queue number register is coupled to a queue size look-up table (LUT), which provides a queue size value in response to the contents of the queue number register. The queue size value indicates the amount of memory (e.g., the number of memory blocks) to be included in each of the N queues. The queue size value is provided to a queue start/end address generator, which automatically generates the start and end address associated with each queue in response to the queue size value. These start and end addresses are stored in queue address register files, which enable proper memory read/write and flag counter operations.
摘要翻译：提供了使用设备的现有引脚将期望数量的队列（N）加载到队列号寄存器中的多队列FIFO存储器设备。队列号寄存器被耦合到队列大小查询表（LUT），其响应于队列号寄存器的内容提供队列大小值。队列大小值指示要包括在每个N个队列中的存储器量（例如，存储器块的数量）。队列大小值被提供给队列开始/结束地址生成器，其响应于队列大小值自动生成与每个队列相关联的开始和结束地址。这些开始和结束地址存储在队列地址寄存器文件中，这样可以实现适当的存储器读/写和标志计数器操作。

2. 发明申请

US20060018177A1 Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system 有权
标题翻译：多个计数器可以缓解多队列先进先出的内存系统中的标志限制
公开(公告)号：US20060018177A1
公开(公告)日：2006-01-26
申请号：US11040892
申请日：2005-01-21
申请人： Mario Au , Jason Mo
发明人： Mario Au , Jason Mo
IPC分类号： G11C8/00
CPC分类号： G06F5/065 , G06F5/14 , G11C8/16
摘要： A method of operating a multi-queue device, including: (1) storing a plurality of read (write) count pointers, wherein each of the read (write) count pointers is associated with a corresponding queue of the multi-queue device, (2) providing a read (write) count pointer associated with a present queue to read (write) flag logic, (3) adjusting the read (write) count pointer associated with the present queue in response to each read (write) operation performed by the present queue, (4) indicating a read (write) queue switch from the present queue to a next queue, (5) retrieving a read (write) count pointer associated with the next queue; and then (6) simultaneously providing the read (write) count pointer associated with the present queue and the read (write) count pointer associated with the next queue to the read (write) flag logic.
摘要翻译：一种操作多队列设备的方法，包括：（1）存储多个读取（写入）计数指针，其中读取（写入）计数指针中的每一个与多队列设备的相应队列相关联（ 2）提供与当前队列相关联的读取（写入）计数指针以读取（写入）标志逻辑，（3）响应于由每个读取（写入）操作执行的每个读取（写入）操作，调整与当前队列相关联的读取（写入）计数指针（4）指示从当前队列到下一队列的读（写）队列切换，（5）检索与下一队列相关联的读（写）计数指针; 然后（6）同时将与当前队列相关联的读（写）计数指针和与下一队列相关联的读（写）计数指针提供给读（写）标志逻辑。

3. 发明申请

US20060018176A1 Mark/re-read and mark/re-write operations in a multi-queue first-in first-out memory system 有权
公开(公告)号：US20060018176A1
公开(公告)日：2006-01-26
申请号：US11040637
申请日：2005-01-21
申请人： Mario Au , Jason Mo
发明人： Mario Au , Jason Mo
IPC分类号： G11C8/00
CPC分类号： G11C19/287 , G06F5/065 , G06F5/14
摘要： In a multi-queue memory system, a plurality of read count pointers (one for each queue) are stored in a read address file, and used to generate empty flags. A read count pointer associated with a first queue is retrieved from the read address file, and it is determined whether the first queue should be available for a re-read operation. If so, the retrieved read count pointer is stored as a first read mark value. The read count pointer is incremented in response to each read operation performed from the first queue, thereby creating an adjusted read count pointer. If a re-read operation is to be performed from the first queue, the first read mark value is stored in the read address file. Otherwise, the adjusted first read count pointer is stored in the read address file. Similar operations are performed on the write side of the multi-queue memory system.

4. 发明申请

US20060020741A1 Synchronization of active flag and status bus flags in a multi-queue first-in first-out memory system 有权
标题翻译：多队列先进先出存储器系统中的活动标志和状态总线标志的同步
公开(公告)号：US20060020741A1
公开(公告)日：2006-01-26
申请号：US11040804
申请日：2005-01-21
申请人： Mario Au , Jason Mo , Cheng-Han Wu
发明人： Mario Au , Jason Mo , Cheng-Han Wu
IPC分类号： G06F12/00
CPC分类号： G06F5/065 , G06F5/14
摘要： A flag logic circuit includes a first comparator configured to generate a first flag value associated with an active read queue of a multi-queue memory device, and a second comparator configured to generate a second flag value associated with an active write queue of the multi-queue memory device. A dual-port memory is adapted to store a flag value for each queue of the multi-queue memory device. The dual-port memory has a first write port configured to receive the first flag value and a second write port configured to receive the second flag value. A first stage storage element is configured to latch each of the flag values stored in the dual-port memory in response to a first clock signal, such that the flag values are synchronized on an active status bus and flag status bus.
摘要翻译：标志逻辑电路包括：第一比较器，被配置为产生与多队列存储器件的主动读取队列相关联的第一标志值;以及第二比较器，被配置为生成与多队列存储器件的主动读取队列相关联的第二标志值，队列存储设备。双端口存储器适于存储多队列存储器设备的每个队列的标志值。双端口存储器具有被配置为接收第一标志值的第一写入端口和被配置为接收第二标志值的第二写入端口。第一级存储元件被配置为响应于第一时钟信号来锁存存储在双端口存储器中的每个标志值，使得标志值在活动状态总线和标志状态总线上同步。

5. 发明申请

US20060018170A1 Interleaving memory blocks to relieve timing bottleneck in a multi-queue first-in first-out memory system 有权
公开(公告)号：US20060018170A1
公开(公告)日：2006-01-26
申请号：US11040895
申请日：2005-01-21
申请人： Mario Au , Jason Mo , Ta-Chung Ma , Lan Lin
发明人： Mario Au , Jason Mo , Ta-Chung Ma , Lan Lin
IPC分类号： G11C7/00
CPC分类号： G11C19/287 , G11C7/08 , G11C7/1042
摘要： A multi-queue memory system includes first and second memory blocks. The first memory block includes a first array of memory cells, a first sense amplifier circuit and a second sense amplifier circuit. The second memory block includes a second array of memory cells, a third sense amplifier circuit and a fourth sense amplifier circuit. Each of the sense amplifier circuits is independently controlled. Each queue of the multi-queue system has entries in both the first and second memory blocks. A first queue is accessed by alternately accessing the first and second arrays via the first and third sense amplifier circuits. A second queue is subsequently accessed by alternately accessing the first and second arrays via the second and fourth sense amplifier circuits.

6. 发明申请

US20060017497A1 Self-timed multiple blanking for noise suppression during flag generation in a multi-queue first-in first-out memory system 有权
公开(公告)号：US20060017497A1
公开(公告)日：2006-01-26
申请号：US11040927
申请日：2005-01-21
申请人： Jason Mo , Mario Au
发明人： Jason Mo , Mario Au
IPC分类号： H03B1/00
CPC分类号： G11C19/287
摘要： A write counter provides a write count value synchronized with a write clock signal. A read counter provides a read count value synchronized with a read clock signal. The read and write count values are routed through logic, which introduces noise to these values. A first delay circuit generates a first blanking signal, which has a duration corresponding with the duration of the noise introduced to the write count value, in response to the write clock signal. A second delay circuit generates a second blanking signal, which has a duration corresponding with the duration of the noise introduced to the read count value, in response to the second clock signal. The read and write count values are latched into read and write blanking registers, respectively, in response to the first and second blanking signals, respectively, effectively filtering the introduced noise prior to a subsequently performed comparison operation.

7. 发明申请

US20060155940A1 Multi-queue FIFO memory systems that utilize read chip select and device identification codes to control one-at-a-time bus access between selected FIFO memory chips 审中-公开
标题翻译：多队列FIFO存储器系统，利用读取芯片选择和器件识别代码来控制所选FIFO存储器芯片之间的一对一总线访问
公开(公告)号：US20060155940A1
公开(公告)日：2006-07-13
申请号：US11044413
申请日：2005-01-27
申请人： Mario Au , Jason Mo
发明人： Mario Au , Jason Mo
IPC分类号： G06F13/00
CPC分类号： G06F5/065
摘要： Multi-Q FIFO memory systems include a plurality of multi-Q first-in first-out (FIFO) memory chips electrically coupled to a data output bus. The plurality of multi-Q FIFO memory chips, which are responsive to respective identification codes ID and respective read chip select signals (/RCS), are configured to support an enhanced multi-chip expansion mode of operation. This expansion mode of operation uses the read chip select signals to control one-at-a-time access of at least two selected multi-Q FIFO memory chips receiving equivalent ID codes and equivalent read addresses to the output data bus during read operations.
摘要翻译：多Q FIFO存储器系统包括电耦合到数据输出总线的多个多Q先进先出（FIFO）存储器芯片。响应于各个识别码ID和各个读取芯片选择信号（/ RCS）的多个多Q FIFO存储器芯片被配置为支持增强的多芯片扩展操作模式。这种扩展操作模式使用读取芯片选择信号来控制在读取操作期间将至少两个选择的多Q FIFO存储器芯片在接收等效的ID代码和等同的读取地址一次访问输出数据总线。

8. 发明申请

US20060020761A1 Partial packet read/write and data filtering in a multi-queue first-in first-out memory system 有权
标题翻译：多队列先进先出存储器系统中的部分数据包读/写和数据过滤
公开(公告)号：US20060020761A1
公开(公告)日：2006-01-26
申请号：US11040896
申请日：2005-01-21
申请人： Mario Au , Jason Mo , Hui Su
发明人： Mario Au , Jason Mo , Hui Su
IPC分类号： G06F12/14
CPC分类号： G06F5/065 , G06F2205/108
摘要： A multi-queue memory system is configured to operate in a packet mode. Each packet includes a SOP (start of packet) marker and an EOP (end of packet) marker. A packet status bit (PSB), is used to implement the packet mode. The packet status bit enables partial packet write and partial packet read operations, such that a queue switch can be performed in the middle of packet write or packet read operations. The packet status bit also enables data filtering to be performed between an activated EOP marker and a subsequently received SOP marker (i.e., between the end of one packet and the start of the next packet). Packet mark and re-write and packet mark and re-read operations are also enabled.
摘要翻译：多队列存储器系统被配置为以分组模式操作。每个分组包括SOP（分组开始）标记和EOP（分组结束）标记。分组状态位（PSB）用于实现分组模式。分组状态位使得能够进行部分分组写入和部分分组读取操作，使得可以在分组写入或分组读取操作的中间执行队列切换。分组状态位还使得能够在激活的EOP标记和随后接收的SOP标记（即，在一个分组的结束和下一个分组的开始之间）之间执行数据过滤。数据包标记和重写以及数据包标记和重新读取操作也被启用。

9. 发明申请

US20060020742A1 Status bus accessing only available quadrants during loop mode operation in a multi-queue first-in first-out memory system 有权
标题翻译：在多队列先进先出存储器系统中，状态总线仅在循环模式操作期间仅访问可用象限
公开(公告)号：US20060020742A1
公开(公告)日：2006-01-26
申请号：US11040893
申请日：2005-01-21
申请人： Mario Au , Jason Mo , Cheng-Han Wu
发明人： Mario Au , Jason Mo , Cheng-Han Wu
IPC分类号： G06F12/00
CPC分类号： G06F5/065
摘要： A flag logic circuit is provided for use in a multi-queue memory device having a plurality of queues. A first stage memory stores a flag value for each of the queues in the multi-queue memory device. Flag values are routed from the first stage memory to a flag status bus having a width N in the manner described below. A status bus control circuit receives a signal that identifies the number of queues M actually used by the multi-queue memory device, and in response, generates a repeating pattern of X control values, wherein X is equal to (M−(M mod N))/N+1. A selector circuit sequentially routes X sets of N flag values from the first stage memory to the flag status bus in response to the repeating pattern of X control values. The X sets of N flag values include the flag values associated with the queues actually used.
摘要翻译：提供了一种用于具有多个队列的多队列存储装置中的标志逻辑电路。第一级存储器存储多队列存储器设备中的每个队列的标志值。标志值以下述方式从第一级存储器路由到具有宽度N的标志状态总线。状态总线控制电路接收识别由多队列存储装置实际使用的队列数M的信号，并且作为响应，生成X个控制值的重复模式，其中X等于（M-（M mod N ））/ N + 1。响应于X控制值的重复模式，选择器电路将X组N标志值从第一级存储器顺序路由到标志状态总线。 X组N标志值包括与实际使用的队列相关联的标志值。

10. 发明授权

US07944876B2 Time slot interchange switch with bit error rate testing 有权
标题翻译：时隙互换开关，具有误码率测试
公开(公告)号：US07944876B2
公开(公告)日：2011-05-17
申请号：US11143010
申请日：2005-06-01
申请人： Jason Mo
发明人： Jason Mo
IPC分类号： H04L12/50 , H04W4/00 , H04Q11/00
CPC分类号： H04L43/50
摘要： In accordance with the invention, time slot interchange switches (“TSIS”) with bit error rate testing are described. The bit error rate testing includes creating a channel of data appropriate for bit error rate testing and monitoring the bit error rate testing on that channel.
摘要翻译：根据本发明，描述了具有误码率测试的时隙交换开关（“TSIS”）。误码率测试包括创建适合于误码率测试的数据通道，并监视该通道上的误码率测试。

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