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1. 发明申请

US20070288882A1 Methods and apparatus for simulating distributed effects 有权
标题翻译：用于模拟分布效应的方法和装置
公开(公告)号：US20070288882A1
公开(公告)日：2007-12-13
申请号：US11524655
申请日：2006-09-21
申请人： Margaret L. Kniffin , Dmitry S. Shipitsin , Michael J. Zunino
发明人： Margaret L. Kniffin , Dmitry S. Shipitsin , Michael J. Zunino
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5036
摘要： In general, various embodiments of the present invention relate to systems and methods for simulating distributed effects by providing a meshing pattern (200) (e.g., a two-dimensional meshing pattern that is part of a recognition layer), applying that meshing pattern to the physical layout (100), and partitioning the physical layout into a three-dimensional netlist (300) of components derived from the unit cells defined by the meshing pattern (200), thereby modeling the parasitics within the design.
摘要翻译：通常，本发明的各种实施例涉及通过提供网格图案（200）（例如，作为识别层的一部分的二维啮合图案）来模拟分布效应的系统和方法，将该网格图案应用于物理布局（100），以及将所述物理布局分割成由所述网格图案（200）定义的单位单元导出的部件的三维网表（300），从而对所述设计内的寄生效果进行建模。

2. 发明授权

US07530039B2 Methods and apparatus for simulating distributed effects 有权
标题翻译：用于模拟分布效应的方法和装置
公开(公告)号：US07530039B2
公开(公告)日：2009-05-05
申请号：US11524655
申请日：2006-09-21
申请人： Margaret L. Kniffin , Dmitry S. Shipitsin , Michael J. Zunino
发明人： Margaret L. Kniffin , Dmitry S. Shipitsin , Michael J. Zunino
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5036
摘要： In general, various embodiments of the present invention relate to systems and methods for simulating distributed effects by providing a meshing pattern (200) (e.g., a two-dimensional meshing pattern that is part of a recognition layer), applying that meshing pattern to the physical layout (100), and partitioning the physical layout into a three-dimensional netlist (300) of components derived from the unit cells defined by the meshing pattern (200), thereby modeling the parasitics within the design.
摘要翻译：通常，本发明的各种实施例涉及通过提供网格图案（200）（例如，作为识别层的一部分的二维啮合图案）来模拟分布效应的系统和方法，将该网格图案应用于物理布局（100），以及将所述物理布局分割成由所述网格图案（200）定义的单位单元导出的部件的三维网表（300），从而对所述设计内的寄生效果进行建模。

3. 发明申请

US20140312457A1 INTEGRATED CIRCUIT CHIP WITH DISCONTINUOUS GUARD RING 有权
标题翻译：集成电路芯片与不连续的保护环
公开(公告)号：US20140312457A1
公开(公告)日：2014-10-23
申请号：US13864729
申请日：2013-04-17
申请人： Qiang Li , Olin L. Hartin , Sateh Jalaleddine , Radu M. Secareanu , Michael J. Zunino
发明人： Qiang Li , Olin L. Hartin , Sateh Jalaleddine , Radu M. Secareanu , Michael J. Zunino
IPC分类号： H01L27/02 , H01L21/76
CPC分类号： H01L27/0203 , H01L21/76 , H01L23/5223 , H01L23/5225 , H01L23/5227 , H01L23/585 , H01L23/645 , H01L27/08 , H01L28/10 , H01L29/402 , H01L29/404 , H01L2924/0002 , H01L2924/00
摘要： An electronic apparatus includes a semiconductor substrate, a circuit block disposed in and supported by the semiconductor substrate and comprising an inductor, and a discontinuous noise isolation guard ring surrounding the circuit block. The discontinuous noise isolation guard ring includes a metal ring supported by the semiconductor substrate and a ring-shaped region disposed in the semiconductor substrate, having a dopant concentration level, and electrically coupled to the metal ring, to inhibit noise in the semiconductor substrate from reaching the circuit. The metal ring has a first gap and the ring-shaped region has a second gap.
摘要翻译：电子设备包括半导体衬底，设置在半导体衬底中并由半导体衬底支撑并包括电感器的电路块以及围绕电路块的不连续噪声隔离保护环。不连续的噪声隔离保护环包括由半导体衬底支撑的金属环和设置在半导体衬底中的环形区域，具有掺杂剂浓度水平并且电耦合到金属环，以抑制半导体衬底中的噪声达到电路。金属环具有第一间隙，并且环形区域具有第二间隙。

4. 发明授权

US08957496B2 Integrated circuit chip with discontinuous guard ring 有权
标题翻译：具有不连续保护环的集成电路芯片
公开(公告)号：US08957496B2
公开(公告)日：2015-02-17
申请号：US13864729
申请日：2013-04-17
申请人： Qiang Li , Olin L. Hartin , Sateh Jalaleddine , Radu M. Secareanu , Michael J. Zunino
发明人： Qiang Li , Olin L. Hartin , Sateh Jalaleddine , Radu M. Secareanu , Michael J. Zunino
IPC分类号： H01L21/70 , H01L21/76 , H01L27/02
CPC分类号： H01L27/0203 , H01L21/76 , H01L23/5223 , H01L23/5225 , H01L23/5227 , H01L23/585 , H01L23/645 , H01L27/08 , H01L28/10 , H01L29/402 , H01L29/404 , H01L2924/0002 , H01L2924/00
摘要： An electronic apparatus includes a semiconductor substrate, a circuit block disposed in and supported by the semiconductor substrate and comprising an inductor, and a discontinuous noise isolation guard ring surrounding the circuit block. The discontinuous noise isolation guard ring includes a metal ring supported by the semiconductor substrate and a ring-shaped region disposed in the semiconductor substrate, having a dopant concentration level, and electrically coupled to the metal ring, to inhibit noise in the semiconductor substrate from reaching the circuit. The metal ring has a first gap and the ring-shaped region has a second gap.
摘要翻译：电子设备包括半导体衬底，设置在半导体衬底中并由半导体衬底支撑并包括电感器的电路块以及围绕电路块的不连续噪声隔离保护环。不连续的噪声隔离保护环包括由半导体衬底支撑的金属环和设置在半导体衬底中的环形区域，具有掺杂剂浓度水平并且电耦合到金属环，以抑制半导体衬底中的噪声达到电路。金属环具有第一间隙，并且环形区域具有第二间隙。

5. 发明授权

US4914051A Method for making a vertical power DMOS transistor with small signal bipolar transistors 失效
标题翻译：制造具有小信号双极晶体管的垂直功率DMOS晶体管的方法
公开(公告)号：US4914051A
公开(公告)日：1990-04-03
申请号：US281593
申请日：1988-12-09
申请人： Wing K. Huie , Alexander H. Owens , David S. Pan , Michael J. Zunino
发明人： Wing K. Huie , Alexander H. Owens , David S. Pan , Michael J. Zunino
IPC分类号： H01L21/28 , H01L21/761 , H01L21/8249 , H01L27/06
CPC分类号： H01L29/66712 , H01L21/28 , H01L21/761 , H01L21/8249 , H01L27/0623 , H01L29/7302 , H01L29/7322 , H01L29/7809 , H01L29/0696 , Y10S148/126
摘要： A silicon integrated circuit includes a vertical power DMOS transistor and a vertical NPN transistor in separate epitaxial pockets by a method including simultaneously forming a plurality of D-well regions in the DMOS transistor and the base region in the NPN transistor, and including simultaneously forming the elemental source regions and the emitter region. N-type buried layers are provided simultaneously in the DMOS and the NPN transistors, respectively. Also formed simultaneously are two N+ plugs connecting the two buried layers, respectively, to the epitaxial surface of the integrated circuit die. None of these economically attractive simultaneous steps requires deviation in either device from optimum geometries. Also disclosed are compatible and integrated steps for forming small signal CMOS transistors. This method also includes a full self-alignment of gate, source and channel regions in the DMOS transistor as well as in the CMOS transistors.
摘要翻译：硅集成电路通过包括在DMOS晶体管和NPN晶体管中的基极区域中同时形成多个D阱区域的方法，在单独的外延阱中包括垂直功率DMOS晶体管和垂直NPN晶体管，并且包括同时形成元素源极区域和发射极区域。分别在DMOS和NPN晶体管中同时提供N型掩埋层。同时形成两个分别将两个掩埋层连接到集成电路管芯的外延表面的N +插头。这些经济上有吸引力的同步步骤都不需要任何装置的偏差与最佳几何形状。还公开了用于形成小信号CMOS晶体管的兼容和集成步骤。该方法还包括DMOS晶体管以及CMOS晶体管中的栅极，源极和沟道区域的完全自对准。

6. 发明授权

US6110804A Method of fabricating a semiconductor device having a floating field conductor 失效
标题翻译：制造具有浮动场导体的半导体器件的方法
公开(公告)号：US6110804A
公开(公告)日：2000-08-29
申请号：US887718
申请日：1997-07-07
申请人： Vijay Parthasarathy , Michael J. Zunino , William R. Peterson , Shang-Hui Tu
发明人： Vijay Parthasarathy , Michael J. Zunino , William R. Peterson , Shang-Hui Tu
IPC分类号： H01L29/06 , H01L29/40 , H01L29/78 , H01L21/76
CPC分类号： H01L29/404 , H01L29/7835
摘要： A semiconductor device (10) uses a plurality of floating field conductors (26, 28) to provide a substantially uniform electric field along the surface of the drift region (17) of the device (10). This substantially uniform electric field increases the breakdown voltage per unit length of the drift region (17).
摘要翻译：半导体器件（10）使用多个浮动场导体（26,28）沿着器件（10）的漂移区域（17）的表面提供基本均匀的电场。该基本上均匀的电场增加漂移区（17）的每单位长度的击穿电压。

7. 发明授权

US4646124A Level shifting BIMOS integrated circuit 失效
标题翻译：电平转换BIMOS集成电路
公开(公告)号：US4646124A
公开(公告)日：1987-02-24
申请号：US635867
申请日：1984-07-30
申请人： Michael J. Zunino
发明人： Michael J. Zunino
IPC分类号： H01L27/06 , H01L27/092 , H03K17/567 , H01L27/02 , H01L27/04
CPC分类号： H03K17/567 , H01L27/0623 , H01L27/092
摘要： An integrated circuit has small signal MOS logic transistors formed in an N-type basket which basket itself is formed in an N-type epitaxial pocket that is defined by an enclosing P-type isolation wall. In a second epitaxial pocket a relatively high-current carrying bipolar transistor is formed. The MOS containing N-type basket is tied to one DC voltage which the substrate and isolation walls are connected to a lower level DC voltage. Substrate currents that are caused by the high current in the bipolar transistor are prevented by the N-type basket from inducing voltage changes in the MOS transistors.
摘要翻译：集成电路具有形成在N型篮中的小信号MOS逻辑晶体管，其篮子本身形成在由封闭的P型隔离壁限定的N型外延袋中。在第二外延袋中，形成相对高电流的双极晶体管。含有N型篮的MOS晶体管连接到一个直流电压，基板和隔离壁连接到较低的直流电压。由双极晶体管中的高电流引起的衬底电流被N型筐阻止从MOS晶体管的电压变化引起。

8. 发明授权

US08729954B2 MOFSET mismatch characterization circuit 有权
标题翻译： MOFSET不匹配表征电路
公开(公告)号：US08729954B2
公开(公告)日：2014-05-20
申请号：US13222323
申请日：2011-08-31
申请人： Colin C. McAndrew , Michael J. Zunino
发明人： Colin C. McAndrew , Michael J. Zunino
IPC分类号： H03K17/687
CPC分类号： H01L22/34 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising a first inverter circuit including a first PMOS transistor and a first NMOS transistor, a drain electrode of the first PMOS transistor coupled to a drain electrode of the first NMOS transistor, and a second inverter circuit including a second PMOS transistor and a second NMOS transistor, a drain electrode of the second PMOS transistor coupled to a drain electrode of the second NMOS transistor. A first output voltage pad coupled to gate electrodes of the first and second PMOS and NMOS transistors, and between the drain electrode of the first PMOS transistor and the drain electrode of the NMOS transistor to self-bias the first inverter circuit. A second output voltage pad coupled between the drain electrode of the second PMOS transistor and the drain electrode of the second NMOS transistor.
摘要翻译：一种半导体器件，包括：第一反相器电路，包括第一PMOS晶体管和第一NMOS晶体管;第一PMOS晶体管的漏电极，耦合到第一NMOS晶体管的漏极;以及第二反相器电路，包括第二PMOS晶体管和第二NMOS晶体管，第二PMOS晶体管的漏电极耦合到第二NMOS晶体管的漏电极。第一输出电压焊盘，其耦合到第一和第二PMOS和NMOS晶体管的栅电极，并且在第一PMOS晶体管的漏电极和NMOS晶体管的漏电极之间，以自偏压第一反相器电路。耦合在第二PMOS晶体管的漏电极和第二NMOS晶体管的漏电极之间的第二输出电压焊盘。

9. 发明申请

US20130049852A1 MOFSET MISMATCH CHARACTERIZATION CIRCUIT 有权
标题翻译： MOFSET MISMATCH特征电路
公开(公告)号：US20130049852A1
公开(公告)日：2013-02-28
申请号：US13222323
申请日：2011-08-31
申请人： COLIN C. MCANDREW , Michael J. Zunino
发明人： COLIN C. MCANDREW , Michael J. Zunino
IPC分类号： H01L25/07 , H01L21/28
CPC分类号： H01L22/34 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising a first inverter circuit including a first PMOS transistor and a first NMOS transistor, a drain electrode of the first PMOS transistor coupled to a drain electrode of the first NMOS transistor, and a second inverter circuit including a second PMOS transistor and a second NMOS transistor, a drain electrode of the second PMOS transistor coupled to a drain electrode of the second NMOS transistor. A first output voltage pad coupled to gate electrodes of the first and second PMOS and NMOS transistors, and between the drain electrode of the first PMOS transistor and the drain electrode of the NMOS transistor to self-bias the first inverter circuit. A second output voltage pad coupled between the drain electrode of the second PMOS transistor and the drain electrode of the second NMOS transistor.
摘要翻译：一种半导体器件，包括：第一反相器电路，包括第一PMOS晶体管和第一NMOS晶体管;第一PMOS晶体管的漏电极，耦合到第一NMOS晶体管的漏极;以及第二反相器电路，包括第二PMOS晶体管和第二NMOS晶体管，第二PMOS晶体管的漏电极耦合到第二NMOS晶体管的漏电极。第一输出电压焊盘，其耦合到第一和第二PMOS和NMOS晶体管的栅电极，并且在第一PMOS晶体管的漏电极和NMOS晶体管的漏电极之间，以自偏压第一反相器电路。耦合在第二PMOS晶体管的漏电极和第二NMOS晶体管的漏电极之间的第二输出电压焊盘。

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