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1. 发明授权

US08170420B2 Changing hardware settings based on data preamble 有权
标题翻译：根据数据前导码改变硬件设置
公开(公告)号：US08170420B2
公开(公告)日：2012-05-01
申请号：US12206231
申请日：2008-09-08
申请人： Marcus Schorpp , Markus Muller , Dirk Uffmann
发明人： Marcus Schorpp , Markus Muller , Dirk Uffmann
IPC分类号： H04B10/00 , H04B1/00
CPC分类号： H04L25/4902 , H04W28/18 , H04W28/22 , H04W52/0229 , H04W88/06
摘要： The present invention provides a new and unique method and apparatus for a new data speed switching scheme for a wired data interface. The method features receiving high-speed serial data over a physical link using a first coding scheme in a receiver; receiving a transmission mode change signal transmitted with sequential information about a change in a data transmission mode of the receiver using a second coding scheme and switching the data transmission mode of the receiver in response thereto. The data transmission modes may include at least one low-power mode where no data transmission is possible and the receiver is powered down. The at least one low-power mode may include two different power down states, each having different wake-up times. The data transmission modes may also include at least one high speed mode where data transmission is possible and the receiver is on. The at least one high speed mode may include several high speed modes, each having different data transmission rates.
摘要翻译：本发明提供了一种用于有线数据接口的新的数据速度切换方案的新颖且唯一的方法和装置。该方法特征在接收机中使用第一编码方案在物理链路上接收高速串行数据; 接收利用第二编码方式接收与接收机的数据发送模式有关的变化的顺序信息而发送的发送模式变更信号，并对其进行接收的数据发送模式的切换。数据传输模式可以包括至少一个低功率模式，其中不能进行数据传输并且接收机断电。至少一个低功率模式可以包括两个不同的掉电状态，每个具有不同的唤醒时间。数据传输模式还可以包括至少一个高速模式，其中数据传输是可能的并且接收器处于打开状态。至少一个高速模式可以包括几种高速模式，每种模式具有不同的数据传输速率。

2. 发明授权

US07017048B2 Circuit configuration for generating current pulses in the supply current of integrated circuits 失效
公开(公告)号：US07017048B2
公开(公告)日：2006-03-21
申请号：US10021689
申请日：2001-11-13
申请人： Otto Schneider , Dirk Uffmann
发明人： Otto Schneider , Dirk Uffmann
IPC分类号： H04L9/32
CPC分类号： G06K19/0701 , G06K19/0723 , G06K19/073 , H03K5/12 , H03K17/284 , H03K17/6872
摘要： Differential power analysis on an integrated circuit is made more difficult by providing a circuit configuration for generating current pulses in the supply current of the integrated circuit. These additional pulses that are generated in the supply current are synchronous with the edges of the internal clock signal of the integrated circuit. In this case, the pulse shape and also the amplitude and the time profile are similar to the pulses in the supply current which are generated by other circuit sections, for example by processors or by some other digital logic, and in digital circuits, typically correspond to a charging curve of a capacitor via a resistor. The circuit generates these additional pulses by using a delay element.

3. 发明授权

US06876226B2 Integrated digital circuit 有权
标题翻译：集成数字电路
公开(公告)号：US06876226B2
公开(公告)日：2005-04-05
申请号：US10372721
申请日：2003-02-24
申请人： Michael Buchmann , Dirk Uffmann
发明人： Michael Buchmann , Dirk Uffmann
IPC分类号： G11C11/22 , G11C16/02 , H03K3/356 , H03K19/173
CPC分类号： G11C11/22 , G11C13/0004
摘要： The invention relates to an integrated digital circuit comprising a logic circuit portion which takes one of at least two different logic states in accordance with provided control signals. In order to minimize the power consumption and to enable a fast start up of the circuit resuming the previous states, it is proposed that it further comprises a non-volatile storage component. The non-volatile storage component takes one of at least two different logic states based on a non-destructive programming, and keeps a programmed logic state for a basically unlimited time and independently of a power supply until a new programming occurs, and is programmed by each change of the logic state of the logic circuit portion. The invention relates equally to a device comprising such a digital circuit and to a method of operating such a digital circuit.
摘要翻译：本发明涉及一种集成数字电路，其包括根据提供的控制信号采取至少两种不同逻辑状态中的一种的逻辑电路部分。为了最小化功耗并且能够快速启动恢复先前状态的电路，建议进一步包括非易失性存储组件。非易失性存储组件基于非破坏性编程获得至少两种不同的逻辑状态中的一种，并且将编程逻辑状态保持在基本上无限制的时间并且独立于电源直到新的编程发生，并且由逻辑电路部分的逻辑状态的每个变化。本发明同样涉及包括这种数字电路的装置以及操作这种数字电路的方法。

4. 发明授权

US06479871B2 Electrostatic discharge (ESD) latch-up protective circuit for an integrated circuit 失效
标题翻译：用于集成电路的静电放电（ESD）闭锁保护电路
公开(公告)号：US06479871B2
公开(公告)日：2002-11-12
申请号：US09833353
申请日：2001-04-12
申请人： Christian Peters , Dirk Uffmann , Hans-Heinrich Viehmann
发明人： Christian Peters , Dirk Uffmann , Hans-Heinrich Viehmann
IPC分类号： H01L2362
CPC分类号： H01L27/0251 , H01L27/0259
摘要： The ESD protective circuit proceeds from a modified lateral pnpn “latch-up” protective structure having a highly doped n-type zone, which is arranged on the well boundary, along that section of the periphery of the well which runs between the two oppositely doped regions. The highly doped zone is formed of pads arranged with intermediate spacing along the section of the periphery of the well. The result is a low triggering voltage in conjunction with a low on resistance.
摘要翻译： ESD保护电路从修改的侧面pnpn“闩锁”保护结构进行，该保护结构具有高度掺杂的n型区域，该区域布置在阱边界上，沿着井的周边部分在两相对掺杂地区。高掺杂区域由沿着阱的周边部分间隔布置的焊盘形成。结果是低触发电压和低导通电阻。

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