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1. 发明授权

US07372141B2 Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides 有权
标题翻译：半导体堆叠封装组件，其在上侧和下侧具有暴露的衬底表面
公开(公告)号：US07372141B2
公开(公告)日：2008-05-13
申请号：US11395529
申请日：2006-03-31
申请人： Marcos Karnezos , Il Kwon Shim , Byung Joon Han , Kambhampati Ramakrishna , Seng Guan Chow
发明人： Marcos Karnezos , Il Kwon Shim , Byung Joon Han , Kambhampati Ramakrishna , Seng Guan Chow
IPC分类号： H01L23/02 , H01L21/00 , H05K1/14
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/552 , H01L24/73 , H01L25/03 , H01L25/105 , H01L25/16 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/73204 , H01L2224/73265 , H01L2224/85013 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2225/1088 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15311 , H01L2924/16195 , H01L2924/181 , H01L2924/1815 , H01L2924/19105 , H01L2924/19106 , H01L2924/19107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： Stacked package assemblies include first and second stacked packages, each having at least one die affixed to, and electrically interconnected with, a die attach side of the package substrate. One package is inverted in relation to the other, that is, the die attach sides of the package substrates face one another, and the “land” sides of the substrates face away from one another. Z-interconnection of the packages is by wire bonds connecting the first and second package substrates. The assembly is encapsulated in such a way that both the second package substrate (one side of the assembly) and a portion of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made. One or more additional components may be stacked over the land side of the first package substrate.
摘要翻译：堆叠的封装组件包括第一和第二堆叠封装，每个封装具有至少一个管芯，该裸管固定到封装衬底的管芯附着侧并与其电连接。一个封装相对于另一个封装反转，即，封装基板的管芯附接面彼此面对，并且基板的“焊盘”侧面彼此背离。封装的Z-互连是通过连接第一和第二封装衬底的引线键合。组件以这样的方式封装，使得第二封装衬底（组件的一侧）和第一封装衬底的一部分（在组件的相对侧）被暴露，使得第二级互连和互连可以制造组件。一个或多个附加部件可以堆叠在第一封装基板的接地侧上。

2. 发明授权

US07429787B2 Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides 有权
标题翻译：半导体组件包括芯片级封装和第二衬底，其上和下侧具有暴露表面
公开(公告)号：US07429787B2
公开(公告)日：2008-09-30
申请号：US11397027
申请日：2006-03-31
申请人： Marcos Karnezos , IL Kwon Shim , Byung Joon Han , Kambhampati Ramakrishna , Seng Guan Chow
发明人： Marcos Karnezos , IL Kwon Shim , Byung Joon Han , Kambhampati Ramakrishna , Seng Guan Chow
IPC分类号： H01L23/02 , H01L21/00 , H05K1/14
CPC分类号： H01L23/3128 , H01L21/563 , H01L23/3135 , H01L23/49575 , H01L23/49833 , H01L23/552 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/162 , H01L2224/05553 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/0652 , H01L2225/06568 , H01L2225/06572 , H01L2225/06586 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01013 , H01L2924/10162 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15311 , H01L2924/16195 , H01L2924/181 , H01L2924/19107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Semiconductor assemblies include a first package, each having at least one die affixed to, and electrically interconnected with, a die attach side of the first package substrate, and a second substrate having a first side and a second (“land”) side, mounted over the molding of the first package with the first side of the second substrate facing the die attach side of the first package substrate. Z-interconnection of the package and the substrate is by wire bonds connecting the first and second substrates. The assembly is encapsulated with both the land side of the second substrate and a portion of the land side of the first package substrate exposed, so that second level interconnection and interconnection with additional components may be made.
摘要翻译：半导体组件包括：第一封装，每个封装具有至少一个管芯，其固定到第一封装衬底的管芯附着侧并与之电互连，以及具有第一侧面和第二（“焊盘”）侧的第二衬底，在第一封装的模制中，第二衬底的第一面面向第一封装衬底的裸片附着侧。封装和基板的Z形互连是通过连接第一和第二基板的引线键合。组件被封装在第二衬底的接地侧和第一封装衬底的接地侧的一部分之间，从而可以形成第二级互连和与附加部件的互连。

3. 发明申请

US20060220209A1 Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides 有权
公开(公告)号：US20060220209A1
公开(公告)日：2006-10-05
申请号：US11395529
申请日：2006-03-31
申请人： Marcos Karnezos , Il Shim , Byung Han , Kambhampati Ramakrishna , Seng Chow
发明人： Marcos Karnezos , Il Shim , Byung Han , Kambhampati Ramakrishna , Seng Chow
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/552 , H01L24/73 , H01L25/03 , H01L25/105 , H01L25/16 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/73204 , H01L2224/73265 , H01L2224/85013 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2225/1088 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15311 , H01L2924/16195 , H01L2924/181 , H01L2924/1815 , H01L2924/19105 , H01L2924/19106 , H01L2924/19107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： Stacked package assemblies include first and second stacked packages, each having at least one die affixed to, and electrically interconnected with, a die attach side of the package substrate. One package is inverted in relation to the other; that is, the die attach sides of the package substrates face one another, and the “land” sides of the substrates face away from one another. Z-interconnection of the packages is by wire bonds connecting the first and second package substrates. The assembly is encapsulated in such a way that both the second package substrate (one side of the assembly) and a portion of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made. In some embodiments the first package is a chip scale package, and the second package is a land grid array package. Also, methods for making such stacked packages assemblies include steps of providing a cavity molded LGA package, preferably tested as “good”; applying an adhesive onto the surface of the mold cap of the LGA package; providing a singulated CSP; inverting the CSP and placing the inverted CSP onto the adhesive on the LGA mold cap; curing the adhesive; performing a plasma clean; wire bonding to form z-interconnection between the die attach side of the LGA and the land side of the CSP; performing a plasma clean; performing a molding operation to enclose the die attach side of the LGA, the z-interconnection wire bonds and wire loops, the edges of the CSP, and the marginal area on the land side of the CSP, leaving exposed the land side of the LGA substrate and an area of the land side of the CSP substrate located within a marginal area; attaching second level interconnect solder balls to sites on exposed area of the CSP substrate; and (where the LGA package was provided in a strip or array) saw singulating to complete the assembly. In some embodiments one or more additional components are stacked over the land side of the LGA substrate.

4. 发明申请

US20060220210A1 Semiconductor assembly including chip scale package and second substrate and having exposed substrate surfaces on upper and lower sides 有权
公开(公告)号：US20060220210A1
公开(公告)日：2006-10-05
申请号：US11397027
申请日：2006-03-31
申请人： Marcos Karnezos , Il Shim , Byung Han , Kambhampati Ramakrishna , Seng Chow
发明人： Marcos Karnezos , Il Shim , Byung Han , Kambhampati Ramakrishna , Seng Chow
IPC分类号： H01L23/02
CPC分类号： H01L23/3128 , H01L21/563 , H01L23/3135 , H01L23/49575 , H01L23/49833 , H01L23/552 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/162 , H01L2224/05553 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/0652 , H01L2225/06568 , H01L2225/06572 , H01L2225/06586 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01013 , H01L2924/10162 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15311 , H01L2924/16195 , H01L2924/181 , H01L2924/19107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Semiconductor assemblies include a first package, each having at least one die affixed to, and electrically interconnected with, a die attach side of the first package substrate, and a second substrate having a first side and a second (“land”) side, mounted over the molding of the first package with the first side of the second substrate facing the die attach side of the first package substrate. Accordingly, the die attach sides of the first substrate and the first side of the second substrate face one another, and the “land” sides of the substrates face away from one another. Z-interconnection of the package and the substrate is by wire bonds connecting the first and second substrates. The assembly is encapsulated in such a way that both the land side of the second substrate (one side of the assembly) and a portion of the land side of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made. In some embodiments the first package is a chip scale package. Also, methods for making such stacked packages assemblies include steps of providing singulated CSP; applying an adhesive onto the surface of the molding of the CSP; providing a second substrate having first and second sides; inverting the CSP and placing the inverted CSP onto the first side of the second substrate such that the adhesive contacts the first side of the second substrate; curing the adhesive; performing a plasma clean; wire bonding to form z-interconnection between the first side of the second substrate and the land side of the CSP; performing a plasma clean; performing a molding operation to enclose the first side of the second substrate, the z-interconnection wire bonds and wire loops, the edges of the CSP, and the marginal area on the land side of the CSP, leaving exposed the land side of the second substrate and an area of the land side of the CSP substrate located within a marginal area; attaching second level interconnect solder balls to sites on exposed area of the CSP substrate; and (where the second substrate was provided in a strip or array) saw singulating to complete the assembly. In some embodiments one or more additional components are stacked over the land side of the second substrate.

5. 发明授权

US08030756B2 Plastic ball grid array package with integral heatsink 有权
标题翻译：塑料球栅阵列封装，带集成散热片
公开(公告)号：US08030756B2
公开(公告)日：2011-10-04
申请号：US11697433
申请日：2007-04-06
申请人： Taekeun Lee , Flynn Carson , Marcos Karnezos
发明人： Taekeun Lee , Flynn Carson , Marcos Karnezos
IPC分类号： H01L23/10
CPC分类号： H01L21/565 , H01L23/3128 , H01L23/3142 , H01L23/4334 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A plastic ball grid array semiconductor package employs a metal heat spreader having supporting arms embedded in the molding cap, in which the embedded supporting arms are not directly affixed to the substrate or in which any supporting arm that is affixed to the substrate is affixed using a resilient material such as an elastomeric adhesive. Also, a process for forming the package includes steps of placing the heat spreader in a mold cavity, placing the substrate over the mold cavity such that the die support surface of the substrate contacts the supporting arms of the heat spreader, and injecting the molding material into the cavity to form the molding cap. The substrate is positioned in register over the mold cavity such that as the molding material hardens to form the mold cap the embedded heat spreader becomes fixed in the appropriate position in relation to the substrate.
摘要翻译：塑料球栅阵列半导体封装采用金属散热器，其具有嵌入在成型帽中的支撑臂，其中嵌入的支撑臂不直接固定到基板上，或者使用附接到基板的任何支撑臂弹性粘合剂如弹性材料。此外，用于形成包装的方法包括以下步骤：将散热器放置在模腔中，将基板放置在模腔上，使得基板的模具支撑表面接触散热器的支撑臂，并且将模制材料进入模腔以形成模制帽。基板被定位在模腔上，使得当模制材料硬化以形成模具盖时，嵌入式散热器相对于基板固定在适当的位置。

6. 发明授权

US07829382B2 Method for making semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package 有权
标题翻译：制造半导体多功能封装的方法，包括堆叠在球栅阵列封装上的裸片和倒置的栅格阵列封装
公开(公告)号：US07829382B2
公开(公告)日：2010-11-09
申请号：US12699787
申请日：2010-02-03
申请人： Marcos Karnezos , Flynn Carson , Youngcheol Kim
发明人： Marcos Karnezos , Flynn Carson , Youngcheol Kim
IPC分类号： H01L21/00 , H01L23/02 , H05K5/00
CPC分类号： H01L25/03 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/48227 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2225/06562 , H01L2225/06568 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for making a multipackage module that has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die.
摘要翻译：一种用于制造具有各种类型的多个管芯并具有各种功能的多包层模块的方法，并且在一些实施例中，该模块包括数字处理器，模拟设备和存储器。具有相对较大占地面积的第一模具安装在第一封装衬底的表面上的第一裸片附着区域上。具有明显更小的占地面积的第二模具安装在第一模具的表面上，朝向第一模具的一个边缘的第二芯片附接区域上。第一裸片通过引线键合连接到衬底的芯片附接侧中的导电迹线。第二管芯通过引线接合电连接到第一封装衬底，并且还可以通过引线电连接到第一管芯。

7. 发明授权

US07645634B2 Method of fabricating module having stacked chip scale semiconductor packages 有权
标题翻译：制造具有堆叠芯片级半导体封装的模块的方法
公开(公告)号：US07645634B2
公开(公告)日：2010-01-12
申请号：US12125770
申请日：2008-05-22
申请人： Marcos Karnezos
发明人： Marcos Karnezos
IPC分类号： H01L21/00 , H01L23/02
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/3135 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/03 , H01L25/105 , H01L25/16 , H01L25/167 , H01L2224/05553 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06575 , H01L2225/06586 , H01L2225/1023 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2924/00014 , H01L2924/10162 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15311 , H01L2924/15331 , H01L2924/16195 , H01L2924/181 , H01L2924/19105 , H01L2924/19107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Stacked CSP (chip scale package) modules include a molded first (“top”) chip scale package having a molding side and a substrate side, and a second (“bottom”) package affixed to the substrate side of the top chip scale package, the second package being electrically connected to the first package by wire bonding between the first and second package substrates.
摘要翻译：堆叠CSP（芯片尺寸封装）模块包括具有成型侧和基板侧的成型的第一（“顶部”）芯片尺寸封装和固定到顶部芯片级封装的基板侧的第二（“底部”）封装，所述第二封装通过所述第一和第二封装衬底之间的引线接合而电连接到所述第一封装。

8. 发明授权

US07589407B2 Semiconductor multipackage module including tape substrate land grid array package stacked over ball grid array package 有权
标题翻译：半导体多功能封装模块，包括堆叠在球栅阵列封装上的带状衬底焊盘栅格阵列封装
公开(公告)号：US07589407B2
公开(公告)日：2009-09-15
申请号：US11396954
申请日：2006-04-03
申请人： Marcos Karnezos
发明人： Marcos Karnezos
IPC分类号： H01L23/02
CPC分类号： H01L23/3128 , H01L23/49816 , H01L23/49861 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A single metal layer tape substrate includes a patterned metal layer affixed to a patterned dielectric layer. The dielectric layer is patterned to provide openings exposing lands and bond sites on bond fingers on the land side of the metal layer. The metal layer is patterned to provide circuit traces as appropriate for interconnection with the die (on the die attach side) and with other elements (such as other packages in a multi-package module). Interconnection with a die is made by wire bonding to exposed traces on a die attach side of the metal layer, and bond fingers and lands for access to testing the package are provided on the opposite (land) side of the metal layer. In some embodiments a row of wire bond sites on the land side of adjacent bond fingers is exposed by a common opening in the dielectric layer, providing for a finer pitch interconnect and, accordingly, a higher interconnect density between stacked packages. Also a land grid array package having such a single metal layer tape substrate. Also, a multi-package module including such a single metal layer tape substrate land grid array package stacked over a ball grid array package. Methods for making the substrate are also disclosed.
摘要翻译：单个金属层带基板包括固定到图案化电介质层上的图案化金属层。对电介质层进行图案化以提供在金属层的接地侧上的接合指状物上的接合区和接合位置的开口。金属层被图案化以提供适合于与管芯（管芯附接侧）和其它元件（例如多封装模块中的其它封装）的互连的电路迹线。通过引线接合到金属层的管芯附着侧上的暴露的迹线，并且在金属层的相对（平台）侧上设置用于接合测试封装的接合指状物和焊盘的区域来实现与管芯的互连。在一些实施例中，相邻接合指的陆地侧上的一排引线接合位置被介电层中的公共开口暴露，从而提供更细的间距互连，并因此提供堆叠封装之间的更高互连密度。还有一种具有这种单一金属层带基片的平面阵列阵列封装。而且，包括堆叠在球栅阵列封装上的这样的单个金属层带衬底焊盘栅格阵列封装的多封装模块。还公开了制备基底的方法。

9. 发明申请

US20080179733A1 SEMICONDUCTOR MULTI-PACKAGE MODULE INCLUDING TAPE SUBSTRATE LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE 有权
标题翻译：半导体多包装模块，其中包括带状基板土地网格阵列堆叠在球网阵列上
公开(公告)号：US20080179733A1
公开(公告)日：2008-07-31
申请号：US12059077
申请日：2008-03-31
申请人： Marcos Karnezos
发明人： Marcos Karnezos
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L23/3128 , H01L23/49816 , H01L23/49861 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A single metal layer tape substrate includes a patterned metal layer affixed to a patterned dielectric layer. The dielectric layer is patterned to provide openings exposing lands and bond sites on bond fingers on the land side of the metal layer. The metal layer is patterned to provide circuit traces as appropriate for interconnection with the die and with other elements. Interconnection with a die is made by wire bonding to exposed traces on a die attach side of the metal layer, and bond fingers and lands for access to testing the package are provided on the land side of the metal layer.
摘要翻译：单个金属层带基板包括固定到图案化电介质层上的图案化金属层。对电介质层进行图案化以提供在金属层的接地侧上的接合指状物上的接合区和接合位置的开口。金属层被图案化以提供适合于与管芯和其它元件的互连的电路迹线。通过引线接合到金属层的管芯附着侧上的暴露的迹线，并且在金属层的陆侧上设置用于接触测试封装的接合指状物和焊盘来进行与管芯的互连。

10. 发明授权

US07351610B2 Method of fabricating a semiconductor multi-package module having a second package substrate with an exposed metal layer wire bonded to a first package substrate 有权
标题翻译：一种制造具有第二封装基板的半导体多封装模块的方法，该第二封装基板具有接合到第一封装基板上的暴露的金属层引线
公开(公告)号：US07351610B2
公开(公告)日：2008-04-01
申请号：US11622993
申请日：2007-01-12
申请人： Marcos Karnezos
发明人： Marcos Karnezos
IPC分类号： H01L21/48 , H01L23/02 , B23K31/02
CPC分类号： H01L23/4334 , H01L21/563 , H01L23/3128 , H01L23/36 , H01L23/552 , H01L24/73 , H01L25/03 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/32225 , H01L2224/48 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06572 , H01L2225/06589 , H01L2225/1005 , H01L2225/1023 , H01L2225/1052 , H01L2225/1058 , H01L2225/1094 , H01L2924/01013 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/1433 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/16152 , H01L2924/181 , H01L2924/19105 , H01L2924/19107 , H01L2924/30107 , H01L2924/3025 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor multi-package module has stacked first and second packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the first and second substrates are interconnected by wire bonding, and in which the first package includes a flip-chip ball grid array package having a flip-chip in a die-up configuration. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a flip-chip in a die-up configuration, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
摘要翻译：半导体多封装模块具有堆叠的第一和第二封装，每个封装包括附接到基板的管芯，其中第二封装反相，其中第一和第二基板通过引线接合互连，并且其中第一封装封装包括具有倒装置的倒装芯片的倒装芯片球栅阵列封装。另外，制造半导体多封装模块的方法是通过提供包括下基板和倒装芯片在内的倒装置的下模制封装，将包括反向取向的上基板的上模制封装固定在上模下封装的表面，并且在上基板和下基板之间形成z-互连。

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