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1. 发明申请

US20070075785A1 PHASE LOCKED LOOP AND METHOD FOR ADJUSTING THE FREQUENCY AND PHASE IN THE PHASE LOCKED LOOP 有权
标题翻译：相位锁定环路和相位锁定环路中的频率和相位调整方法
公开(公告)号：US20070075785A1
公开(公告)日：2007-04-05
申请号：US11469423
申请日：2006-08-31
申请人： Marcel Kossel , Thomas Morf , Martin Schmatz , Silvan Wehrli
发明人： Marcel Kossel , Thomas Morf , Martin Schmatz , Silvan Wehrli
IPC分类号： H03L7/00
CPC分类号： H03L7/093 , H03L7/089 , H03L7/18
摘要： A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.
摘要翻译：一种锁相环（PLL），其包括与时间数字转换器耦合的相位频率检测器，其能够将参考信号与振荡器信号进行比较，并产生表示参考信号和振荡器信号之间的相位差的数字值。 PLL还包括能够根据数字值产生控制值的相位获取状态机，以及能够根据控制值产生振荡器信号的可控振荡器。

2. 发明申请

US20050111536A1 Method for determining jitter of a signal in a serial link and high speed serial link 有权
标题翻译：用于确定串行链路和高速串行链路中的信号抖动的方法
公开(公告)号：US20050111536A1
公开(公告)日：2005-05-26
申请号：US10720974
申请日：2003-11-24
申请人： Hayden Cranford , Marcel Kossel , Vernon Norman , Martin Schmatz
发明人： Hayden Cranford , Marcel Kossel , Vernon Norman , Martin Schmatz
IPC分类号： H04B3/46 , H04L1/20 , H04L25/06
CPC分类号： H04L25/068 , H04B3/462 , H04L1/205
摘要： The method for determining jitter of a signal in a serial link according to the invention comprising the following steps: First, a section of the signal transmitted via a transmission channel is sampled at different sampling times. The total number of edges in the section is determined. The neighboring sample values are analyzed and from that a statistical value is formed. From the statistical value and the total number of edges a figure of merit is determined. Finally, by means of a look-up table or a jitter-versus-figure of merit curve, the total jitter corresponding to the figure of merit is derived.
摘要翻译：根据本发明的用于确定串行链路中的信号的抖动的方法包括以下步骤：首先，经由传输信道发送的信号的一部分在不同的采样时间被采样。确定该部分中的边缘总数。分析相邻的样本值，并从中形成统计值。从统计值和总边缘数确定品质因数。最后，通过查询表或优点曲线的抖动对数值，推导出与品质因数对应的总抖动。

3. 发明申请

US20070286190A1 Transmitter-receiver crossbar for a packet switch 审中-公开
标题翻译：分组交换机的发射机 - 接收机交叉开关
公开(公告)号：US20070286190A1
公开(公告)日：2007-12-13
申请号：US11803803
申请日：2007-05-16
申请人： Wolfgang Denzel , Ronald Luijten , Thomas Morf , Martin Schmatz
发明人： Wolfgang Denzel , Ronald Luijten , Thomas Morf , Martin Schmatz
IPC分类号： H04L12/56
CPC分类号： H04L49/101
摘要： A transmitter-receiver crossbar for a packet switch comprising a transmitter having an array of transmitting ports, each having one or more transmitting antennas to transmit a radio signal and a receiver having an array of receiving ports, each having one or more receiving antennas to receive the radio signal.
摘要翻译：一种用于分组交换机的发射机 - 接收机交叉开关，包括具有发射端口阵列的发射机，每个发射端口具有一个或多个发射天线以发射无线电信号，以及具有接收端阵列的接收机，每个接收端口具有一个或多个接收天线以接收无线电信号。

4. 发明授权

US06981168B2 Clock data recovery system 有权
标题翻译：时钟数据恢复系统
公开(公告)号：US06981168B2
公开(公告)日：2005-12-27
申请号：US10284547
申请日：2002-10-30
申请人： Martin Schmatz , Christian Menofli , Thomas Morf
发明人： Martin Schmatz , Christian Menofli , Thomas Morf
IPC分类号： H03K5/1534 , H03L7/093 , H04L7/033 , G06F1/04
CPC分类号： H03L7/093 , H03K5/1534 , H04L7/033
摘要： A clock data recovery system is provided for resampling a clock signal according to an incoming data signal stream. It comprises a clock generator for generating said clock signal wherein one of the frequency and phase of that clock signal is dependent upon a control signal. It is further provided a phase detector operable to detect the phase difference between said clock signal and said incoming data signal stream and is operable to generate a phase difference signal. A loop controller has a variable-gain and is operable to control said clock generator by generating said control signal. That control signal is dependent in said phase difference signal and that variable-gain. The variable-gain is dependent upon a transition rate of the incoming data signal stream. The loop controller can comprise a low-pass filter to generate from the phase difference signal a low-pass filered phase signal and to adjust the bandwidth of the clock data recovery system. The loop controller further can comprise a variable-gain element to amplify the filtered signal in accordance with a received bit transition rate provided by a bit transition detector and a density calculator.
摘要翻译：提供时钟数据恢复系统，用于根据输入数据信号流重新采样时钟信号。它包括用于产生所述时钟信号的时钟发生器，其中该时钟信号的频率和相位之一取决于控制信号。还提供了一种相位检测器，可操作以检测所述时钟信号和所述输入数据信号流之间的相位差，并可操作以产生相位差信号。环路控制器具有可变增益，并且可操作以通过产生所述控制信号来控制所述时钟发生器。该控制信号依赖于所述相位差信号和该可变增益。可变增益取决于输入数据信号流的转换速率。环路控制器可以包括低通滤波器，以从相位差信号产生低通档案相位信号并调整时钟数据恢复系统的带宽。环路控制器还可以包括可变增益元件，以根据由位跃迁检测器和密度计算器提供的接收位转换速率来放大经滤波的信号。

5. 发明申请

US20060008042A1 Analog unidirectional serial link architecture 有权
标题翻译：模拟单向串行链路架构
公开(公告)号：US20060008042A1
公开(公告)日：2006-01-12
申请号：US11225600
申请日：2005-09-13
申请人： Hayden Cranford , Stacy Garvin , Vernon Norman , Paul Owczarski , Martin Schmatz , Joseph Stevens
发明人： Hayden Cranford , Stacy Garvin , Vernon Norman , Paul Owczarski , Martin Schmatz , Joseph Stevens
IPC分类号： H03D3/24
CPC分类号： H03L7/0995 , H04L7/0004 , H04L7/0337
摘要： The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.
摘要翻译：本发明涉及包括逻辑发射机部分和逻辑接收机部分的统一数字架构。提供了一种用于在包括发射机和接收机部分的有线媒体上传输数字数据的统一的串行链路系统和方法，发射机部分和接收机部分之一包括锁相环（PLL）电路。 PLL电路包括压控振荡器，分频器，相频检测器，电荷泵和多极环路滤波器。一个实施例包括具有数字粗略回路和模拟精细回路的双回路PLL。

6. 发明授权

US07447278B2 Apparatus for transmitting and receiving data 失效
标题翻译：用于发送和接收数据的装置
公开(公告)号：US07447278B2
公开(公告)日：2008-11-04
申请号：US10849693
申请日：2004-05-20
申请人： Christian Menolfi , Martin Schmatz , Thomas Toifl
发明人： Christian Menolfi , Martin Schmatz , Thomas Toifl
IPC分类号： H03D1/00
CPC分类号： H04L25/03343 , H04L7/0334 , H04L25/0272 , H04L25/068 , H04L25/49 , H04L25/497 , H04L2025/03477 , H04L2025/03802 , H04L2025/03808
摘要： The apparatus for transmitting and receiving data according to the invention contains a transmitter (1) for serial data transmission and a receiver (3) for receiving a transmitted data signal (g(t)). The receiver (3) in turn comprises a first sample latch (11) for sampling the received data signal (g(t)) with a first clock (f2) and for generating a first sample value (an). The receiver (3) also comprises a second sample latch (13) for sampling a first shifted received data signal (g(t)+V1) with a second clock (f1) and for generating a second sample value (yn). The receiver (3) further comprises a third sample latch (14) for sampling a second shifted received data signal (g(t)−V1) with the second clock (f1) and for generating a third sample value (zn). Finally the receiver (3) comprises a logic unit (15) for recovering data (dn) out of said first, second and third sample values (an, yn, zn).
摘要翻译：根据本发明的用于发送和接收数据的装置包括用于串行数据传输的发射机（1）和用于接收发射数据信号（g（t））的接收机（3）。接收器（3）又包括用于利用第一时钟（f 2）对接收到的数据信号（g（t））进行采样并用于产生第一采样值（a）的第一采样锁存器（11）。接收器（3）还包括用于利用第二时钟（f 1）对第一移位的接收数据信号（g（t）+ V 1）进行采样并用于产生第二采样值（yn）的第二采样锁存器（13）。接收器（3）还包括用于利用第二时钟（f 1）对第二移位的接收数据信号（g（t）-V 1）进行采样并用于产生第三采样值（zn）的第三采样锁存器（14）。最后，接收器（3）包括用于从所述第一，第二和第三采样值（an，yn，zn）中恢复数据（dn）的逻辑单元（15）。

7. 发明申请

US20070242741A1 One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery 失效
标题翻译：单采样每位决策反馈均衡器（DFE）时钟和数据恢复
公开(公告)号：US20070242741A1
公开(公告)日：2007-10-18
申请号：US11405997
申请日：2006-04-18
申请人： Juan Carballo , Hayden Cranford , Gareth Nicholls , Vernon Norman , Martin Schmatz
发明人： Juan Carballo , Hayden Cranford , Gareth Nicholls , Vernon Norman , Martin Schmatz
IPC分类号： H03H7/30
CPC分类号： H04L25/03063
摘要： Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.
摘要翻译：公开了一种在接收机中利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的接收器电路，方法和设计架构，并且降低了误码率（BER ）。集成接收机与决策反馈均衡器以及适当的（CDR）环路相位检测器相结合，以保持每位需求的单个采样。输入电压被转换为电流并连接到电流求和节点。由先前检测到的位及其各自的反馈系数的值确定的加权电流也连接到该节点。另外，总和电流被积分并转换成电压。采样器用于基于所得到的电压进行位决定。采样后，积分器在分析下一位之前被复位。通过使用在数据锁存器前面的积分来最大化锁存器的灵敏度来实现必要的放大。

8. 发明申请

US20070101086A1 System, method and storage medium for deriving clocks in a memory system 失效
标题翻译：用于在存储器系统中导出时钟的系统，方法和存储介质
公开(公告)号：US20070101086A1
公开(公告)日：2007-05-03
申请号：US11263344
申请日：2005-10-31
申请人： Frank Ferraiolo , Kevin Gower , Martin Schmatz
发明人： Frank Ferraiolo , Kevin Gower , Martin Schmatz
IPC分类号： G06F13/00
CPC分类号： G06F13/4234 , G06F13/1689
摘要： A system, method and storage medium for deriving clocks in a memory system. The method includes receiving a reference oscillator clock at a hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.
摘要翻译：一种用于在存储器系统中导出时钟的系统，方法和存储介质。该方法包括在集线器装置处接收参考振荡器时钟。集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。以基准时钟频率工作的基本时钟从参考振荡器时钟导出。通过将基本时钟乘以存储器乘法器导出存储器接口时钟。控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。

9. 发明申请

US20060029177A1 Unified digital architecture 失效
公开(公告)号：US20060029177A1
公开(公告)日：2006-02-09
申请号：US11249851
申请日：2005-10-13
申请人： Hayden Cranford , Vernon Norman , Martin Schmatz
发明人： Hayden Cranford , Vernon Norman , Martin Schmatz
IPC分类号： H03D3/24
CPC分类号： H03L7/08 , H03L7/095 , H03L7/0995 , H03L7/10 , H04L7/0337 , H04L2027/0067
摘要： A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.

10. 发明申请

US20050002475A1 Apparatus for transmitting and receiving data 失效
标题翻译：用于发送和接收数据的装置
公开(公告)号：US20050002475A1
公开(公告)日：2005-01-06
申请号：US10849693
申请日：2004-05-20
申请人： Christian Menolfi , Martin Schmatz , Thomas Toifl
发明人： Christian Menolfi , Martin Schmatz , Thomas Toifl
IPC分类号： H04L7/033 , H04L25/02 , H04L25/03 , H04L25/06 , H04L25/49 , H04L25/497 , H03D1/00
CPC分类号： H04L25/03343 , H04L7/0334 , H04L25/0272 , H04L25/068 , H04L25/49 , H04L25/497 , H04L2025/03477 , H04L2025/03802 , H04L2025/03808
摘要： The apparatus for transmitting and receiving data according to the invention contains a transmitter (1) for serial data transmission and a receiver (3) for receiving a transmitted data signal (g(t)). The receiver (3) in turn comprises a first sample latch (11) for sampling the received data signal (g(t)) with a first clock (f2) and for generating a first sample value (an). The receiver (3) also comprises a second sample latch (13) for sampling a first shifted received data signal (g(t)+V1) with a second clock (f1) and for generating a second sample value (yn). The receiver (3) further comprises a third sample latch (14) for sampling a second shifted received data signal (g(t)−V1) with the second clock (f1) and for generating a third sample value (zn). Finally the receiver (3) comprises a logic unit (15) for recovering data (dn) out of said first, second and third sample values (an, yn, zn).
摘要翻译：根据本发明的用于发送和接收数据的装置包括用于串行数据传输的发射机（1）和用于接收发射数据信号（g（t））的接收机（3）。接收器（3）又包括用于利用第一时钟（f2）对接收到的数据信号（g（t））进行采样并用于产生第一采样值（a）的第一采样锁存器（11）。接收器（3）还包括用于利用第二时钟（f1）对第一移位的接收数据信号（g（t）+ V1）进行采样并用于生成第二采样值（yn）的第二采样锁存器（13）。接收机（3）还包括第三采样锁存器（14），用于对第二时钟（f1）采样第二移位接收数据信号（g（t）-V1）并产生第三采样值（zn）。最后，接收器（3）包括用于从所述第一，第二和第三采样值（an，yn，zn）中恢复数据（dn）的逻辑单元（15）。

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