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1. 发明授权

US08745419B2 Logical power throttling of instruction decode rate for successive time periods 有权
标题翻译：连续时间段的逻辑功率节制指令解码速率
公开(公告)号：US08745419B2
公开(公告)日：2014-06-03
申请号：US13529761
申请日：2012-06-21
申请人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
发明人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
IPC分类号： G06F1/32 , G06F9/30
CPC分类号： G06F9/3867 , G06F1/206 , G06F1/3203 , G06F9/3869 , Y02D10/16
摘要： A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.
摘要翻译：处理器包括提供节流功率输出信号的装置。节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不会物理地改变处理器周期或任何处理器供电电压。

2. 发明授权

US07500086B2 Start transactional execution (STE) instruction to support transactional program execution 有权
标题翻译：启动事务执行（STE）指令以支持事务性程序执行
公开(公告)号：US07500086B2
公开(公告)日：2009-03-03
申请号：US11296599
申请日：2005-12-06
申请人： Marc Tremblay , Shailender Chaudhry , Quinn A. Jacobson
发明人： Marc Tremblay , Shailender Chaudhry , Quinn A. Jacobson
IPC分类号： G06F9/40 , G06F15/00
CPC分类号： G06F9/528 , G06F9/3004 , G06F9/30087 , G06F9/30116 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3857 , Y10S707/99953
摘要： One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the STE instruction. Changes made during this transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes.
摘要翻译：本发明的一个实施例支持开始事务执行（STE）指令的执行，其指示要在事务上执行的指令块的开始。在执行程序期间遇到STE指令时，系统开始按照STE指令执行指令块的事务性执行。在事务执行之前进行的更改不会在事务执行成功完成之前提交到处理器的体系结构状态。

3. 发明授权

US07418577B2 Fail instruction to support transactional program execution 有权
标题翻译：支持事务性程序执行的失败指令
公开(公告)号：US07418577B2
公开(公告)日：2008-08-26
申请号：US10637169
申请日：2003-08-08
申请人： Marc Tremblay , Shailender Chaudhry , Quinn A. Jacobson
发明人： Marc Tremblay , Shailender Chaudhry , Quinn A. Jacobson
IPC分类号： G06F9/00
CPC分类号： G06F9/3863 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3857
摘要： One embodiment of the present invention provides a system that supports executing a fail instruction, which terminates transactional execution of a block of instructions. During operation, the system facilitates transactional execution of a block of instructions within a program, wherein changes made during the transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes. If a fail instruction is encountered during this transactional execution, the system terminates the transactional execution without committing results of the transactional execution to the architectural state of the processor.
摘要翻译：本发明的一个实施例提供一种支持执行失败指令的系统，其终止指令块的事务执行。在操作期间，系统促进程序内的指令块的事务执行，其中在事务执行期间所做的更改不会被提交到处理器的体系结构状态，直到事务执行成功完成。如果在此事务执行期间遇到失败指令，则系统终止事务执行，而不将事务执行的结果提交给处理器的体系结构状态。

4. 发明申请

US20070226467A1 WORKING REGISTER FILE ENTRIES WITH INSTRUCTION BASED LIFETIME 有权
标题翻译：使用基于生命周期的工作注册文件
公开(公告)号：US20070226467A1
公开(公告)日：2007-09-27
申请号：US11425869
申请日：2006-06-22
申请人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
发明人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A technique for operating a computing apparatus includes allocating a working register file entry corresponding to a register in a working register file when an instruction referencing the register proceeds through a particular stage of the computing apparatus. The technique maintains the working register file entry until at least a predetermined number of subsequent instructions have similarly proceeded through the particular stage.
摘要翻译：一种用于操作计算设备的技术包括：当参考寄存器的指令通过计算设备的特定阶段进行时，分配与工作寄存器文件中的寄存器相对应的工作寄存器文件条目。该技术维持工作寄存器文件条目，直到至少预定数量的后续指令已经类似地进行到特定阶段。

5. 发明申请

US20100191993A1 LOGICAL POWER THROTTLING 有权
标题翻译：逻辑功率曲线
公开(公告)号：US20100191993A1
公开(公告)日：2010-07-29
申请号：US12361422
申请日：2009-01-28
申请人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
发明人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
IPC分类号： G06F1/32 , G06F1/26 , G06F9/30
CPC分类号： G06F9/3867 , G06F1/206 , G06F1/3203 , G06F9/3869 , Y02D10/16
摘要： A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.
摘要翻译：处理器包括提供节流功率输出信号的装置。节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不会物理地改变处理器周期或任何处理器供电电压。

6. 发明授权

US07565511B2 Working register file entries with instruction based lifetime 有权
标题翻译：工作寄存器文件条目与指令生命周期
公开(公告)号：US07565511B2
公开(公告)日：2009-07-21
申请号：US11425869
申请日：2006-06-22
申请人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
发明人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A technique for operating a computing apparatus includes allocating a working register file entry corresponding to a register in a working register file when an instruction referencing the register proceeds through a particular stage of the computing apparatus. The technique maintains the working register file entry until at least a predetermined number of subsequent instructions have similarly proceeded through the particular stage.
摘要翻译：一种用于操作计算设备的技术包括：当参考寄存器的指令通过计算设备的特定阶段进行时，分配与工作寄存器文件中的寄存器相对应的工作寄存器文件条目。该技术维持工作寄存器文件条目，直到至少预定数量的后续指令已经类似地进行到特定阶段。

7. 发明授权

US07509481B2 Patchable and/or programmable pre-decode 有权
标题翻译：可修补和/或可编程预解码
公开(公告)号：US07509481B2
公开(公告)日：2009-03-24
申请号：US11277735
申请日：2006-03-28
申请人： Shailender Chaudhry , Paul Caprioli , Quinn A. Jacobson , Marc Tremblay
发明人： Shailender Chaudhry , Paul Caprioli , Quinn A. Jacobson , Marc Tremblay
IPC分类号： G06F9/00
CPC分类号： G06F9/30145 , G06F9/30174 , G06F9/30196 , G06F9/382 , G06F9/3822 , G06F9/3897
摘要： Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a programmable pre-decode mechanism can be employed to alter the behavior of a processor. For example, pre-decode hints for sequencing, synchronization or speculation control may altered or mappings of ISA instructions to native instructions or operation sequences may be altered. Such techniques may be employed to adapt a processor implementation (in the field) to varying memory models, implementations or interfaces or to varying memory latencies or timing characteristics. Similarly, such techniques may be employed to adapt a processor implementation to correspond to an extended/adapted instruction set architecture. In some realizations, instruction pre-decode functionality may be adapted at processor run-time to handle or mitigate a timing, concurrency or speculation issue. In some realizations, operation of pre-decode may be reprogrammed post-manufacture, at (or about) initialization, or at run-time.
摘要翻译：已经开发了用于在处理器指令处理，排序和执行中提供极大灵活性的机制。特别地，已经发现可以采用可编程预解码机制来改变处理器的行为。例如，用于排序，同步或推测控制的预解码提示可以改变或者将ISA指令映射到本地指令或操作序列可以被改变。可以采用这样的技术来使处理器实现（在现场中）适应于变化的存储器模型，实现或接口或者改变存储器延迟或定时特性。类似地，可以采用这样的技术来使处理器实现适应于扩展/适应的指令集架构。在一些实现中，可以在处理器运行时调整指令预解码功能以处理或减轻定时，并发或推测问题。在某些实现中，可以在（或大约）初始化或运行时在制造后重新编程预解码的操作。

8. 发明授权

US07490229B2 Storing results of resolvable branches during speculative execution to predict branches during non-speculative execution 有权
标题翻译：在投机执行期间存储可分解分支的结果，以在非投机执行期间预测分支
公开(公告)号：US07490229B2
公开(公告)日：2009-02-10
申请号：US11093197
申请日：2005-03-29
申请人： Marc Tremblay , Shailender Chaudhry , Quinn A. Jacobson
发明人： Marc Tremblay , Shailender Chaudhry , Quinn A. Jacobson
IPC分类号： G06F9/00
CPC分类号： G06F9/3844 , G06F9/30105 , G06F9/3838 , G06F9/3842 , G06F9/3863
摘要： One embodiment of the present invention provides a system that facilitates storing results of resolvable branches during speculative execution, and then using the results to predict the same branches during non-speculative execution. During operation, the system executes code within a processor. Upon encountering a stall condition, the system speculatively executes the code from the point of the stall, without committing results of the speculative execution to the architectural state of the processor. Upon encountering a branch instruction that is resolved during speculative execution, the system stores the result of the resolved branch in a branch queue, so that the result can be subsequently used to predict the branch during non-speculative execution.
摘要翻译：本发明的一个实施例提供一种便于在推测性执行期间存储可解析分支的结果的系统，然后在非推测性执行期间使用结果来预测相同的分支。在操作期间，系统在处理器内执行代码。在遇到停顿状态时，系统从失速点推测地执行代码，而不会将推测性执行的结果提交给处理器的体系结构状态。在遇到在推测执行期间解析的分支指令时，系统将解析的分支的结果存储在分支队列中，以便随后可以在非推测性执行期间将结果用于预测分支。

9. 发明授权

US07216202B1 Method and apparatus for supporting one or more servers on a single semiconductor chip 有权
标题翻译：用于在单个半导体芯片上支持一个或多个服务器的方法和装置
公开(公告)号：US07216202B1
公开(公告)日：2007-05-08
申请号：US10787386
申请日：2004-02-24
申请人： Shailender Chaudhry , Marc Tremblay , Quinn A. Jacobson
发明人： Shailender Chaudhry , Marc Tremblay , Quinn A. Jacobson
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F9/3004 , G06F9/3005 , G06F9/30087 , G06F9/30116 , G06F9/528 , G06F12/0815 , G06F2212/507 , G06F2212/681
摘要： One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.
摘要翻译：本发明的一个实施例提供一种通过推测性地执行代码的关键部分来有助于避免锁定的系统。在操作期间，系统允许进程在程序中推测性地执行代码的关键部分而不首先获得与关键部分相关联的锁定。如果该过程随后完成关键部分而没有遇到来自另一进程的干扰数据访问，则系统进行在推测执行期间所做的更改，并且通过关键部分恢复程序的正常非推测性执行。否则，如果在执行关键部分期间遇到来自其他进程的干扰数据访问，则系统将丢弃在推测执行期间所做的更改，并尝试重新执行临界部分。

10. 发明申请

US20120331314A1 LOGICAL POWER THROTTLING 有权
标题翻译：逻辑功率曲线
公开(公告)号：US20120331314A1
公开(公告)日：2012-12-27
申请号：US13529761
申请日：2012-06-21
申请人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
发明人： Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
IPC分类号： G06F1/32
CPC分类号： G06F9/3867 , G06F1/206 , G06F1/3203 , G06F9/3869 , Y02D10/16
摘要： A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.
摘要翻译：处理器包括提供节流功率输出信号的装置。节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不物理地改变处理器周期或任何处理器供电电压。

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