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1. 发明申请

US20090161721A1 METHOD FOR TESTING A HEAT PIPE AND CORRESPONDING TEST DEVICE 有权
标题翻译：测试热管和相关测试装置的方法
公开(公告)号：US20090161721A1
公开(公告)日：2009-06-25
申请号：US12334742
申请日：2008-12-15
申请人： Marc Gatti , Gerard Nemoz , Bruno Bellin , Christian Pitot
发明人： Marc Gatti , Gerard Nemoz , Bruno Bellin , Christian Pitot
IPC分类号： G01N25/18
CPC分类号： G01K17/00 , F28F2200/005 , H01L23/427 , H01L2924/0002 , H01L2924/00
摘要： The operational reliability of a heat pipe 200 provided for carrying heat dissipated by an electronic component 101 to a heat exchanger 300 is tested by using the heat pipe in the reverse direction, by providing energy in the form of heat at the exchanger 300, and by measuring the propagation time ΔP of the heat from the exchanger to the electronic component. Application to heat pipe tests in onboard computers.
摘要翻译：通过在交换器300处以热的形式提供能量，并且通过在交换器300处以热的形式提供能量，并且通过在热交换器300中以热的形式提供能量，通过在相反方向上使用热管来测试用于将由电子部件101散发的热量传递到热交换器300 测量从交换器到电子部件的热量的传播时间ΔP。应用于车载电脑的热管测试。

2. 发明授权

US08322917B2 Method for testing a heat pipe and corresponding test device 有权
标题翻译：热管及相应试验装置的测试方法
公开(公告)号：US08322917B2
公开(公告)日：2012-12-04
申请号：US12334742
申请日：2008-12-15
申请人： Marc Gatti , Gerard Nemoz , Bruno Bellin , Christian Pitot
发明人： Marc Gatti , Gerard Nemoz , Bruno Bellin , Christian Pitot
IPC分类号： G01K1/16 , G01K25/00
CPC分类号： G01K17/00 , F28F2200/005 , H01L23/427 , H01L2924/0002 , H01L2924/00
摘要： The operational reliability of a heat pipe 200 provided for carrying heat dissipated by an electronic component 101 to a heat exchanger 300 is tested by using the heat pipe in the reverse direction, by providing energy in the form of heat at the exchanger 300, and by measuring the propagation time ΔP of the heat from the exchanger to the electronic component. Application to heat pipe tests in onboard computers.
摘要翻译：通过在交换器300处以热的形式提供能量，并且通过在交换器300处以热的形式提供能量，并且通过在热交换器300中以热的形式提供能量，通过在相反方向上使用热管来测试用于将由电子部件101散发的热量传递到热交换器300 测量从交换器到电子部件的热量的传播时间＆Dgr; P。应用于车载电脑的热管测试。

3. 发明申请

US20090183038A1 METHOD FOR IMPROVING THE INTEGRITY OF COMMUNICATION MEANS 有权
标题翻译：改善通信手段一致性的方法
公开(公告)号：US20090183038A1
公开(公告)日：2009-07-16
申请号：US12328193
申请日：2008-12-04
申请人： Remi Andreoletti , Christian Pitot , Patrice Toillon
发明人： Remi Andreoletti , Christian Pitot , Patrice Toillon
IPC分类号： G06F11/00
CPC分类号： H04L1/22 , H04L1/20
摘要： Embodiments of the invention enable the integrity of data processed by a switch to be guaranteed better than 10−9 undetected erroneous frames per flight hour. To do this, rules for disabling ports are included in the switch management program. These rules include a maximum absolute admissible number of erroneous frames, to a maximum relative rate of admissible erroneous frames and a minimum number of erroneous frames constituting a significance threshold. Random errors are detected at the level of each frame due to the insertion of a CRC. Deterministic or data-dependent errors able to deceive systematically the CRC check are made random by means of a frame index.
摘要翻译：本发明的实施例使得由开关处理的数据的完整性能够比每个飞行小时的10-9个未检测到的错误帧更好地得到保证。为此，交换机管理程序中包含禁用端口的规则。这些规则包括最大绝对允许的错误帧数，允许错误帧的最大相对速率和构成重要阈值的最小错误帧数。由于插入CRC，在每个帧的级别上检测到随机错误。系统地欺骗CRC校验的确定性或依赖于数据的错误是通过帧索引进行随机的。

4. 发明授权

US07447234B2 Method for the reconstitution of messages conveyed by one or more packet-switched transmission networks 有权
标题翻译：用于重建由一个或多个分组交换传输网络传送的消息的方法
公开(公告)号：US07447234B2
公开(公告)日：2008-11-04
申请号：US10446156
申请日：2003-05-28
申请人： Gérard Colas , Christian Pitot
发明人： Gérard Colas , Christian Pitot
IPC分类号： H04J3/24
CPC分类号： H04L49/901 , H04L29/06 , H04L45/00 , H04L45/24 , H04L47/34 , H04L49/90 , H04L49/9094 , H04L69/14 , H04L69/16 , H04L69/166 , H04L69/22 , H04L69/40 , H04W28/06
摘要： This method enables the reconstitution of messages fragmented in packets. It comprises a process for taking a census of the packets made available to a terminal (1) by transmission networks (Na, Nb) and a process for the reassembling of messages from packets listed by the census-taking process. These two processes implement a table of pointers pointing at the packets made available to the terminal (1) by the transmission networks (Na, Nb), sorted out by membership message, said pointers being placed, for each membership message, in a stack according to the order in which the packets that they point at are made available to the terminal (1) and being provided with information or status fields enabling the reporting of doubles or discrepancies between the order in which the packets of a stack are made available and the natural order of the message fragments constituted by the payloads of the packets, and the fate of the packet pointed at during the reassembling process.
摘要翻译：这种方法使得能够重组分组中的分段的消息。它包括通过传输网络（Na，Nb）对终端（1）可用的分组进行普查的过程，以及用于重新组合由普查过程列出的分组的消息的过程。这两个处理实现指向由通过成员资格消除的传输网络（Na，Nb）向终端（1）提供的分组的指针表，对于每个成员消息，所述指针被放置在堆栈中指向他们指向的分组的顺序使得终端（1）可用，并且被提供有信息或状态字段，使得能够报告堆叠的分组的可用顺序与双方之间的双重或差异的报告由分组的有效载荷构成的消息片段的自然顺序以及在重新组装过程中指向的分组的命运。

5. 发明授权

US08179284B2 Device and method for detecting the digital origin of an analogue signal 有权
标题翻译：用于检测模拟信号的数字原点的装置和方法
公开(公告)号：US08179284B2
公开(公告)日：2012-05-15
申请号：US12491821
申请日：2009-06-25
申请人： Christian Pitot , Jacques Phelippeau , Philippe Bieth
发明人： Christian Pitot , Jacques Phelippeau , Philippe Bieth
IPC分类号： G08B23/00
CPC分类号： G08B29/10
摘要： The present invention relates to an alarm management system intended to be carried onboard an aircraft. More precisely, the invention is aimed at improving the certainty level relating to the integrity of the announcements of faults or information intended for the pilot and based on voice syntheses. For this purpose, the present invention proposes a device and a method for detecting the digital origin of an analog signal providing a validity signal (VAL) enabling the voice announcements made to the pilot to be rendered secure.
摘要翻译：本发明涉及一种旨在承载在飞机上的报警管理系统。更准确地说，本发明的目的在于提高与针对飞行员的故障或信息的公告的完整性相关的确定性水平，并且基于语音合成。为此，本发明提出了一种用于检测提供有效信号（VAL）的模拟信号的数字原点的装置和方法，使得能够使对飞行员的声音通知变得安全。

6. 发明授权

US5719577A Low-cost integrable device for the acquisition of electric signals in compliance with the arnic 429 standard 失效
标题翻译：低成本的可集成设备，用于采购符合Arnic 429标准的电信号
公开(公告)号：US5719577A
公开(公告)日：1998-02-17
申请号：US619083
申请日：1996-03-21
申请人： Christian Pitot , Louis Vriz
发明人： Christian Pitot , Louis Vriz
IPC分类号： H03M3/00 , H03M3/02 , H03M1/12
CPC分类号： H03M3/00
摘要： In order to convert an analog signal of digital data transmission into a digital signal, the device embodying the invention comprises a passive analog circuit comprising a capacitor charged by the analog signal via a first resistor, the voltage at the terminals of the capacitor being applied via a second resistor, at the input of a digital circuit comprising a threshold comparator applying, to a flip-flop, a logic signal which is a function of the result of the comparison with a threshold of the voltage at the input, a means for periodically applying at the input a charge or discharge pulse so as to bring the voltage at the input back to the threshold voltage, a counting circuit for periodically determining a number representative of the analog signal, obtained from subtracting the number of discharges from the number of charges.
摘要翻译：为了将数字数据传输的模拟信号转换为数字信号，实施本发明的装置包括无源模拟电路，其包括经由第一电阻器由模拟信号充电的电容器，电容器的端子处的电压经由第二电阻器，在数字电路的输入处，包括阈值比较器的阈值比较器向触发器施加逻辑信号，逻辑信号是与输入端的电压的阈值进行比较的结果的函数，周期性地在输入端施加充电或放电脉冲，以将输入端的电压恢复到阈值电压;计数电路，用于周期性地确定代表模拟信号的数字，该电平从减少电荷数量得到的放电次数。

7. 发明授权

US06943713B1 Process and device for the sequential addressing of the inputs of a multiplexer of a data acquisition circuit 有权
标题翻译：用于数据采集电路的多路复用器的输入的顺序寻址的过程和设备
公开(公告)号：US06943713B1
公开(公告)日：2005-09-13
申请号：US09673666
申请日：2000-03-10
申请人： Christian Pitot , Jean-Michel Chopin
发明人： Christian Pitot , Jean-Michel Chopin
IPC分类号： G06F17/40 , H03M1/00
CPC分类号： G08C15/00
摘要： The systematic, and possibly repeated, acquisition of several distinct quantities for exploitation by a user system by utilizing a multiplexer with staged architecture without all inputs hard-wired. Each multiplexer stage is addressed by an elementary counter chained with elementary counters for addressing lower stages. The multiplexer inputs are scanned by regularly incrementing the chain of counters. If no precaution is taken, all the multiplexer inputs are scanned without considering their possible absences. To remedy this drawback a first elementary counter addresses the first stage of adjustable counting capacity switches, the elementary counters can address intermediate stages of the switches with controllable shunting circuits, and a global counter is reconfigured, at the end of each counting cycle of the first elementary counter, by commands adjusting the first elementary counter capacity, and activating or inhibiting the shunting circuits. The stored commands are a string of instructions executed one by one.
摘要翻译：系统地，可能重复地采集几个不同的数量，以供用户系统利用具有分段架构的多路复用器，而不需要所有输入的硬连线。每个复用器级由基本计数器寻址，用基本计数器链接用于寻址较低级。通过定期递增计数器链来扫描多路复用器输入。如果没有采取预防措施，所有的多路复用器输入都被扫描，而不考虑它们的可能缺席。为了弥补这个缺陷，第一个基本计数器解决了可调计数能力开关的第一阶段，基本计数器可以利用可控制的分流电路解决开关的中间阶段，并且在第一个计数周期的每个计数周期结束时重新配置一个全局计数器基本计数器，通过调整第一基本计数器容量的命令，以及启动或禁止分流电路。存储的命令是逐个执行的指令串。

8. 发明授权

US6046644A Phase-locked loop oscillator formed entirely of logic circuits 失效
标题翻译：锁相环振荡器完全由逻辑电路组成
公开(公告)号：US6046644A
公开(公告)日：2000-04-04
申请号：US165094
申请日：1998-10-02
申请人： Christian Pitot , Michel Prost
发明人： Christian Pitot , Michel Prost
IPC分类号： H03L7/089 , H03L7/099 , H03B5/02 , H03L7/085
CPC分类号： H03L7/089 , H03L7/0995
摘要： Phase-locked loop oscillators that are designed to set the clock rate of electronic circuits based on combinations of logic circuits and to be integrated, at the same time as these electronic circuits, into one and the same chip. There is proposed a phase-locked loop oscillator based purely on combinations of logic circuits so as not to make use of integration techniques different from those used for the electronic circuits based on combinations of logic circuits, for which they are designed to set the clock rate.
摘要翻译：锁相环振荡器被设计为基于逻辑电路的组合来设置电子电路的时钟速率，并且与这些电子电路同时集成到同一个芯片中。提出了一种纯粹基于逻辑电路组合的锁相环振荡器，以便不利用与基于逻辑电路组合的用于电子电路的集成技术不同的集成技术，它们被设计用于设置时钟速率。

9. 发明授权

US5701315A Method and device for protecting the execution of linear sequences of commands performed by a processor 失效
标题翻译：用于保护由处理器执行的线性命令序列的执行的方法和装置
公开(公告)号：US5701315A
公开(公告)日：1997-12-23
申请号：US504113
申请日：1995-07-19
申请人： Christian Pitot , Martinez Michel
发明人： Christian Pitot , Martinez Michel
IPC分类号： G06F12/16 , G06F11/10 , G06F11/28 , G11C29/00
CPC分类号： G06F11/10 , G06F11/1008 , G06F11/28
摘要： A method for detecting errors in a linear sequence of commands executed by a processor and stored in a memory at a predetermined start address, comprises the association of each word in the sequence to a bit of the start address. Before storing each sequence word into the memory, the method determines the value of an unused bit of the word so that the value of the associated bit of the start address will be equal to the result of a predetermined function applied to the bits of the word. When reading a sequence word in said memory, the method compares the result of said function applied to the bits of the word read, with the value of the associated bit of the start address, and transmits an error signal if a difference is detected.
摘要翻译：一种用于检测由处理器执行并存储在存储器中的预定起始地址的命令的线性序列中的错误的方法，包括将序列中的每个字与起始地址的位的关联。在将每个序列字存储到存储器中之前，该方法确定字的未使用位的值，使得起始地址的相关位的值将等于应用于字的位的预定函数的结果。当在所述存储器中读取序列字时，该方法将应用于读取的字的位的所述功能的结果与起始地址的相关位的值进行比较，并且如果检测到差异则发送错误信号。

10. 发明授权

US5375208A Device for managing a plurality of independent queues in a common non-dedicated memory space 失效
标题翻译：用于在公共非专用存储器空间中管理多个独立队列的设备
公开(公告)号：US5375208A
公开(公告)日：1994-12-20
申请号：US872379
申请日：1992-04-23
申请人： Christian Pitot
发明人： Christian Pitot
IPC分类号： G06F5/06 , G06F13/00
CPC分类号： G06F5/065 , G06F2205/066
摘要： A device for managing a plurality of independent queues in a common non-dedicated memory space uses a set of memory space resource use vectors with one vector per managed queue. A vector defines a list of free memory space locations. Read and write pointer registers store the address of memory locations last written or read and a circuit for evaluating the closest successor of these latter memory locations. The device has the advantage of enabling all memory resources to be used, the same resource being usable by any queue.
摘要翻译：用于管理公共非专用存储器空间中的多个独立队列的设备使用一组存储器空间资源使用向量，每个管理队列具有一个向量。向量定义了可用内存空间位置的列表。读写指针寄存器存储最后写入或读取的存储器位置的地址，以及用于评估这些后一个存储器位置的最后继的电路。该设备具有使能所有存储器资源的优点，同一资源可被任何队列使用。

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