专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06467012B1 Method and apparatus using a distributed system structure to support bus-based cache-coherence protocols for symmetric multiprocessors 失效
标题翻译：使用分布式系统结构来支持对称多处理器的基于总线的高速缓存相干协议的方法和装置
公开(公告)号：US06467012B1
公开(公告)日：2002-10-15
申请号：US09350031
申请日：1999-07-08
申请人： Manuel Alvarez , Sanjay Raghunath Deshpande , Peter Dau Geiger , Jeffrey Holland Gruger
发明人： Manuel Alvarez , Sanjay Raghunath Deshpande , Peter Dau Geiger , Jeffrey Holland Gruger
IPC分类号： G06F1300
CPC分类号： G06F12/0813 , G06F12/0811
摘要： A method and apparatus for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. Each of the processors may have multiple caches. The address switch connects to each of the node controllers and to each of the memory subsystems, and each of the memory subsystems connects to the address switch and to each of the node controllers. The node controller receives commands from a master device and queues commands received from a master device. The node controller has a deterministic delay between latching a snooped command broadcast by the address switch and presenting the command to the master devices on the node controller's master device buses. The memory subsystems contain a memory controller and a fixed delay pipe from the address port to the memory controller so that the memory subsystem has a deterministic delay between receiving a command from the address switch and presenting the command to the memory controller. The buses between the master devices, the node controllers, the address switch, and the memory subsystems are operable using a variety of bus protocols.
摘要翻译：提供了一种使用基于总线的高速缓存相干协议的大方向对称多处理器系统的方法和装置。分布式系统结构包含地址交换机，多个存储器子系统以及被组织成由节点控制器支持的一组节点的多个主设备，处理器，I / O代理或相干存储器适配器。每个处理器可以具有多个高速缓存。地址开关连接到每个节点控制器和每个存储器子系统，并且每个存储器子系统连接到地址开关和每个节点控制器。节点控制器从主设备接收命令，并对从主设备接收的命令进行排队。节点控制器在锁存由地址开关广播的窥探命令之间并且将命令呈现给节点控制器主设备总线上的主设备时具有确定性的延迟。存储器子系统包含存储器控制器和从地址端口到存储器控制器的固定延迟管，使得存储器子系统在从地址开关接收命令并将命令呈现给存储器控制器之间具有确定性的延迟。主设备，节点控制器，地址交换机和存储器子系统之间的总线可以使用各种总线协议来操作。

2. 发明授权

US06442597B1 Providing global coherence in SMP systems using response combination block coupled to address switch connecting node controllers to memory 失效
标题翻译：使用响应组合块在SMP系统中提供全球一致性，将块连接到节点控制器到存储器系统
公开(公告)号：US06442597B1
公开(公告)日：2002-08-27
申请号：US09350032
申请日：1999-07-08
申请人： Sanjay Raghunath Deshpande , Peter Dau Geiger
发明人： Sanjay Raghunath Deshpande , Peter Dau Geiger
IPC分类号： G06F15167
CPC分类号： G06F12/0831 , G06F12/0813 , H04Q2213/13097 , H04Q2213/13103 , H04Q2213/13106 , H04Q2213/13107 , H04Q2213/13292 , H04Q2213/1332 , H04Q2213/13322 , H04Q2213/13396
摘要： A distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The address switch connects to each of the node controllers and to each of the memory subsystems, and each of the memory subsystems connects to the address switch and to each of the node controllers. The node controller receives commands from a master device. The buses between the master devices, the node controllers, the address switch, and the memory subsystems are operable using a variety of bus protocols. A response combination block connects to the address switch, to each master device, to each node controller, and to each memory subsystem in order to receive, logically combine/generate, and then transmit command status signals and command response signals associated with commands issued by master devices. The response combination block generates signals based on whether a master device port is in a local cycle during which a master device may issue a command on the master device port and based on whether the data processing system is in a global cycle during which the address switch broadcasts or snoops a command.
摘要翻译：分布式系统结构包含地址交换机，多个存储器子系统和多个主设备，处理器，I / O代理或相干存储器适配器，被组织成由节点控制器支持的一组节点。地址开关连接到每个节点控制器和每个存储器子系统，并且每个存储器子系统连接到地址开关和每个节点控制器。节点控制器从主设备接收命令。主设备，节点控制器，地址交换机和存储器子系统之间的总线可以使用各种总线协议来操作。响应组合块连接到地址交换机，每个主设备，每个节点控制器和每个存储器子系统，以便接收，逻辑地组合/生成，然后发送与命令发出的命令相关联的命令状态信号和命令响应信号主设备。响应组合块基于主设备端口是否在本地周期中产生信号，在该周期期间，主设备可以在主设备端口上发出命令，并且基于数据处理系统是否处于全局周期中，在该周期期间地址切换广播或窥探一个命令。

3. 发明授权

US06725307B1 Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor system 失效
标题翻译：用于通过分布式多总线多处理器系统中的数据功能与地址和控制功能的物理分离来控制数据传输的方法和系统
公开(公告)号：US06725307B1
公开(公告)日：2004-04-20
申请号：US09404280
申请日：1999-09-23
申请人： Manuel Joseph Alvarez, II , Joel Roger Davidson , Sanjay Raghunath Deshpande , Peter Dau Geiger , Lawrence Joseph Powell , Praveen S. Reddy
发明人： Manuel Joseph Alvarez, II , Joel Roger Davidson , Sanjay Raghunath Deshpande , Peter Dau Geiger , Lawrence Joseph Powell , Praveen S. Reddy
IPC分类号： G06F100
CPC分类号： G06F15/17381 , G06F12/0813 , G06F12/0831
摘要： A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. Due to pin limitations that may be caused by large buses, e.g. buses that support a high number of data pins, the node controller may be implemented such that the functionality for its address paths and data paths are implemented in physically separate components, chips, or circuitry, such as a node data controller or a node address controller. In this case, commands may be sent from the node address controller to the node data controller to control the flow of data through a node.
摘要翻译：提供了一种使用基于总线的高速缓存相干协议的大方向对称多处理器系统的分布式系统结构。分布式系统结构包含地址交换机，多个存储器子系统以及被组织成由节点控制器支持的一组节点的多个主设备，处理器，I / O代理或相干存储器适配器。节点控制器从主设备接收命令，与主设备作为另一个主设备或从设备通信，并对从主设备接收的命令进行排队。由于可能由大型总线引起的引脚限制，例如支持大量数据引脚的总线，可以实现节点控制器，使得其地址路径和数据路径的功能在物理上分离的组件，芯片或电路中实现，诸如节点数据控制器或节点地址控制器。在这种情况下，命令可以从节点地址控制器发送到节点数据控制器，以控制通过节点的数据流。

4. 发明授权

US08793556B1 Systems and methods for reclaiming flash blocks of a flash drive 有权
标题翻译：用于回收闪存驱动器闪存块的系统和方法
公开(公告)号：US08793556B1
公开(公告)日：2014-07-29
申请号：US13477845
申请日：2012-05-22
申请人： Philip L. Northcott , Peter Dau Geiger , Jonathan Sadowsky
发明人： Philip L. Northcott , Peter Dau Geiger , Jonathan Sadowsky
IPC分类号： G11C29/00 , G11C11/34 , G11C16/04 , G06F11/10 , G06F12/02
CPC分类号： G06F11/1068 , G06F11/108 , G06F12/0246 , G06F2212/1016 , G06F2212/7205 , G06F2212/7208
摘要： Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.
摘要翻译：装置和方法提供相对较低的不可校正误码率，低写入放大，长寿命，快速和有效的检索以及有效的存储密度，使得可以使用用于企业存储应用的相对便宜的MLC闪存来实现固态驱动器（SSD）。

5. 发明授权

US09176812B1 Systems and methods for storing data in page stripes of a flash drive 有权
标题翻译：用于将数据存储在闪存驱动器的页面条带中的系统和方法
公开(公告)号：US09176812B1
公开(公告)日：2015-11-03
申请号：US13477568
申请日：2012-05-22
申请人： Philip L. Northcott , Peter Dau Geiger , Jonathan Sadowsky
发明人： Philip L. Northcott , Peter Dau Geiger , Jonathan Sadowsky
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/1012 , G06F11/1008 , G06F11/1044 , G06F11/1068 , G06F11/108
摘要： Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application. Data is stored in page stripes. The page stripes can have varying amounts of payload capacity based on selected error correction code strength. Allocation blocks can be divided into journaling cells, correspond to minimum units of data for which a journaling engine or flash translation layer has a logical-to-physical mapping.
摘要翻译：装置和方法提供相对较低的不可校正误码率，低写入放大，长寿命，快速和有效的检索以及有效的存储密度，使得可以使用用于企业存储应用的相对便宜的MLC闪存来实现固态驱动器（SSD）。数据存储在页面条带中。页面条纹可以基于所选择的纠错码强度具有不同量的有效载荷容量。分配块可以分为日志单元，对应于日志引擎或闪存转换层具有逻辑到物理映射的最小数据单元。

6. 发明授权

US08972824B1 Systems and methods for transparently varying error correction code strength in a flash drive 有权
标题翻译：用于在闪存驱动器中透明地改变纠错码强度的系统和方法
公开(公告)号：US08972824B1
公开(公告)日：2015-03-03
申请号：US13477599
申请日：2012-05-22
申请人： Philip L. Northcott , Peter Dau Geiger , Jonathan Sadowsky
发明人： Philip L. Northcott , Peter Dau Geiger , Jonathan Sadowsky
IPC分类号： G11C29/42 , G11C29/54
CPC分类号： G11C29/42 , G06F11/1012 , G06F11/108 , G11C16/349 , G11C29/52 , G11C2029/0411
摘要： Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.
摘要翻译：装置和方法提供相对较低的不可校正误码率，低写入放大，长寿命，快速和有效的检索以及有效的存储密度，使得可以使用用于企业存储应用的相对便宜的MLC闪存来实现固态驱动器（SSD）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式