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1. 发明申请

US20100148153A1 Group III-V devices with delta-doped layer under channel region 审中-公开
标题翻译： III-V族III族掺杂层在通道区下面
公开(公告)号：US20100148153A1
公开(公告)日：2010-06-17
申请号：US12316878
申请日：2008-12-16
申请人： Mantu K. Hudait , Peter G. Tolchinsky , Robert S. Chau , Marko Radosavljevic , Ravi Pillarisetty , Aaron A. Budrevich
发明人： Mantu K. Hudait , Peter G. Tolchinsky , Robert S. Chau , Marko Radosavljevic , Ravi Pillarisetty , Aaron A. Budrevich
IPC分类号： H01L29/78
CPC分类号： H01L29/7784 , H01L29/365 , H01L29/66462
摘要： A group III-V material device has a delta-doped region below a channel region. This may improve the performance of the device by reducing the distance between the gate and the channel region.
摘要翻译： III-V族材料器件在沟道区域下方具有δ掺杂区域。这可以通过减小栅极和沟道区域之间的距离来改善器件的性能。

2. 发明授权

US08278687B2 Semiconductor heterostructures to reduce short channel effects 有权
标题翻译：半导体异质结构减少短路效应
公开(公告)号：US08278687B2
公开(公告)日：2012-10-02
申请号：US12058101
申请日：2008-03-28
申请人： Ravi Pillarisetty , Mantu K. Hudait , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Robert S. Chau
发明人： Ravi Pillarisetty , Mantu K. Hudait , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Robert S. Chau
IPC分类号： H01L29/778
CPC分类号： H01L29/7783 , H01L29/42316 , H01L29/7784
摘要： Semiconductor heterostructures to reduce short channel effects are generally described. In one example, an apparatus includes a semiconductor substrate, one or more buffer layers coupled to the semiconductor substrate, a first barrier layer coupled to the one or more buffer layers, a back gate layer coupled to the first barrier layer wherein the back gate layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the back gate layer having a first bandgap, a second barrier layer coupled to the back gate layer wherein the second barrier layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the second barrier layer having a second bandgap that is relatively larger than the first bandgap, and a quantum well channel coupled to the second barrier layer, the quantum well channel having a third bandgap that is relatively smaller than the second bandgap.
摘要翻译：通常描述用于减少短通道效应的半导体异质结构。在一个示例中，设备包括半导体衬底，耦合到半导体衬底的一个或多个缓冲层，耦合到一个或多个缓冲层的第一势垒层，耦合到第一阻挡层的背栅层，其中背栅层包括III-V族半导体材料，II-VI族半导体材料或其组合，所述背栅层具有第一带隙，耦合到所述背栅层的第二阻挡层，其中所述第二阻挡层包括III- V族半导体材料，II-VI族半导体材料或其组合，所述第二阻挡层具有相对大于所述第一带隙的第二带隙，以及耦合到所述第二阻挡层的量子阱沟道，所述量子阱沟道具有相对小于第二带隙的第三带隙。

3. 发明申请

US20090242873A1 SEMICONDUCTOR HETEROSTRUCTURES TO REDUCE SHORT CHANNEL EFFECTS 有权
标题翻译：减少短路通道效应的半导体异质结构
公开(公告)号：US20090242873A1
公开(公告)日：2009-10-01
申请号：US12058101
申请日：2008-03-28
申请人： Ravi Pillarisetty , Mantu K. Hudait , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Robert S. Chau
发明人： Ravi Pillarisetty , Mantu K. Hudait , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Robert S. Chau
IPC分类号： H01L29/12 , H01L21/338
CPC分类号： H01L29/7783 , H01L29/42316 , H01L29/7784
摘要： Semiconductor heterostructures to reduce short channel effects are generally described. In one example, an apparatus includes a semiconductor substrate, one or more buffer layers coupled to the semiconductor substrate, a first barrier layer coupled to the one or more buffer layers, a back gate layer coupled to the first barrier layer wherein the back gate layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the back gate layer having a first bandgap, a second barrier layer coupled to the back gate layer wherein the second barrier layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the second barrier layer having a second bandgap that is relatively larger than the first bandgap, and a quantum well channel coupled to the second barrier layer, the quantum well channel having a third bandgap that is relatively smaller than the second bandgap.
摘要翻译：通常描述用于减少短通道效应的半导体异质结构。在一个示例中，设备包括半导体衬底，耦合到半导体衬底的一个或多个缓冲层，耦合到一个或多个缓冲层的第一势垒层，耦合到第一阻挡层的背栅层，其中背栅层包括III-V族半导体材料，II-VI族半导体材料或其组合，所述背栅层具有第一带隙，耦合到所述背栅层的第二阻挡层，其中所述第二阻挡层包括III- V族半导体材料，II-VI族半导体材料或其组合，所述第二阻挡层具有相对大于所述第一带隙的第二带隙，以及耦合到所述第二阻挡层的量子阱沟道，所述量子阱沟道具有相对小于第二带隙的第三带隙。

4. 发明授权

US09356099B2 Techniques for forming contacts to quantum well transistors 有权
公开(公告)号：US09356099B2
公开(公告)日：2016-05-31
申请号：US14334636
申请日：2014-07-17
申请人： Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
发明人： Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
IPC分类号： H01L29/15 , H01L29/41 , H01L29/78 , H01L29/66 , H01L29/778 , H01L29/775 , H01L29/417 , H01L29/423 , H01L29/51
CPC分类号： H01L29/7784 , H01L29/151 , H01L29/155 , H01L29/201 , H01L29/205 , H01L29/401 , H01L29/41725 , H01L29/41775 , H01L29/42316 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/775 , H01L29/7783 , H01L29/78
摘要： Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.

5. 发明授权

US08809836B2 Techniques for forming contacts to quantum well transistors 有权
标题翻译：形成与量子阱晶体管接触的技术
公开(公告)号：US08809836B2
公开(公告)日：2014-08-19
申请号：US13758974
申请日：2013-02-04
申请人： Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
发明人： Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
IPC分类号： H01L29/66
CPC分类号： H01L29/7784 , H01L29/151 , H01L29/155 , H01L29/201 , H01L29/205 , H01L29/401 , H01L29/41725 , H01L29/41775 , H01L29/42316 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/775 , H01L29/7783 , H01L29/78
摘要： Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
摘要翻译：公开了用于向半导体异质结构中形成的器件提供低电阻自对准触点的技术。这些技术可以用于例如形成与在III-V和SiGe / Ge材料系统中制造的量子阱晶体管的栅极，源极和漏极区的接触。不同于在源极/漏极接触到栅极之间的相对大的空间的常规接触工艺流程，由本文所描述的技术提供的所得到的源极和漏极触点是自对准的，因为每个触点与栅电极对准并且被隔离通过间隔材料。

6. 发明授权

US08368052B2 Techniques for forming contacts to quantum well transistors 有权
标题翻译：形成与量子阱晶体管接触的技术
公开(公告)号：US08368052B2
公开(公告)日：2013-02-05
申请号：US12646621
申请日：2009-12-23
申请人： Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
发明人： Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
IPC分类号： H01L29/66
CPC分类号： H01L29/7784 , H01L29/151 , H01L29/155 , H01L29/201 , H01L29/205 , H01L29/401 , H01L29/41725 , H01L29/41775 , H01L29/42316 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/775 , H01L29/7783 , H01L29/78
摘要： Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
摘要翻译：公开了用于向半导体异质结构中形成的器件提供低电阻自对准触点的技术。这些技术可以用于例如形成与在III-V和SiGe / Ge材料系统中制造的量子阱晶体管的栅极，源极和漏极区的接触。不同于在源极/漏极接触到栅极之间的相对大的空间的常规接触工艺流程，由本文所描述的技术提供的所得到的源极和漏极触点是自对准的，因为每个触点与栅电极对准并且被隔离通过间隔材料。

7. 发明申请

US20140326953A1 TECHNIQUES FOR FORMING CONTACTS TO QUANTUM WELL TRANSISTORS 审中-公开
标题翻译：形成量子阱晶体管的技术
公开(公告)号：US20140326953A1
公开(公告)日：2014-11-06
申请号：US14334636
申请日：2014-07-17
申请人： Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
发明人： Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
IPC分类号： H01L29/15 , H01L29/417 , H01L29/78
CPC分类号： H01L29/7784 , H01L29/151 , H01L29/155 , H01L29/201 , H01L29/205 , H01L29/401 , H01L29/41725 , H01L29/41775 , H01L29/42316 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/775 , H01L29/7783 , H01L29/78
摘要： Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
摘要翻译：公开了用于向半导体异质结构中形成的器件提供低电阻自对准触点的技术。这些技术可以用于例如形成与在III-V和SiGe / Ge材料系统中制造的量子阱晶体管的栅极，源极和漏极区的接触。不同于在源极/漏极接触到栅极之间的相对大的空间的常规接触工艺流程，由本文所描述的技术提供的所得到的源极和漏极触点是自对准的，因为每个触点与栅电极对准并且被隔离通过间隔材料。

8. 发明申请

US20110147713A1 TECHNIQUES FOR FORMING CONTACTS TO QUANTUM WELL TRANSISTORS 有权
标题翻译：形成量子阱晶体管的技术
公开(公告)号：US20110147713A1
公开(公告)日：2011-06-23
申请号：US12646621
申请日：2009-12-23
申请人： Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
发明人： Ravi Pillarisetty , Benjamin Chu-Kung , Mantu K. Hudait , Marko Radosavljevic , Jack T. Kavalieros , Willy Rachmady , Niloy Mukherjee , Robert S. Chau
IPC分类号： H01L29/66 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7784 , H01L29/151 , H01L29/155 , H01L29/201 , H01L29/205 , H01L29/401 , H01L29/41725 , H01L29/41775 , H01L29/42316 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/775 , H01L29/7783 , H01L29/78
摘要： Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
摘要翻译：公开了用于向半导体异质结构中形成的器件提供低电阻自对准触点的技术。这些技术可以用于例如形成与在III-V和SiGe / Ge材料系统中制造的量子阱晶体管的栅极，源极和漏极区的接触。不同于在源极/漏极接触到栅极之间的相对大的空间的常规接触工艺流程，由本文所描述的技术提供的所得到的源极和漏极触点是自对准的，因为每个触点与栅电极对准并且被隔离通过间隔材料。

9. 发明授权

US07863710B2 Dislocation removal from a group III-V film grown on a semiconductor substrate 有权
标题翻译：从在半导体衬底上生长的III-V族膜剥离
公开(公告)号：US07863710B2
公开(公告)日：2011-01-04
申请号：US12032579
申请日：2008-02-15
申请人： Mantu K. Hudait , Peter G. Tolchinsky , Jack T. Kavalieros , Marko Radosavljevic
发明人： Mantu K. Hudait , Peter G. Tolchinsky , Jack T. Kavalieros , Marko Radosavljevic
IPC分类号： H01L29/20
CPC分类号： H01L21/02664 , H01L21/02381 , H01L21/02433 , H01L21/02461 , H01L21/02463 , H01L21/02532 , H01L21/02546 , H01L21/02549 , H01L21/02686 , H01L21/268
摘要： Dislocation removal from a group III-V film grown on a semiconductor substrate is generally described. In one example, an apparatus includes a semiconductor substrate, a buffer film including a group III-V semiconductor material epitaxially coupled to the semiconductor substrate wherein the buffer film includes material melted by laser pulse irradiation and recrystallized to substantially remove dislocations or defects from the buffer film, and a first semiconductor film epitaxially grown on the buffer film wherein a lattice mismatch exists between the semiconductor substrate and the first semiconductor film.
摘要翻译：通常描述从在半导体衬底上生长的III-V族膜脱离脱落。在一个示例中，一种装置包括半导体衬底，包括外延耦合到半导体衬底的III-V族半导体材料的缓冲膜，其中缓冲膜包括通过激光脉冲照射熔化的材料并重结晶以基本上从缓冲器中去除位错或缺陷膜，以及在所述缓冲膜上外延生长的第一半导体膜，其中在所述半导体衬底和所述第一半导体膜之间存在晶格失配。

10. 发明申请

US20090206324A1 DISLOCATION REMOVAL FROM A GROUP III-V FILM GROWN ON A SEMICONDUCTOR SUBSTRATE 有权
标题翻译：在半导体基板上形成的III-V族薄膜的分离去除
公开(公告)号：US20090206324A1
公开(公告)日：2009-08-20
申请号：US12032579
申请日：2008-02-15
申请人： Mantu K. Hudait , Peter G. Tolchinsky , Jack T. Kavalieros , Marko Radosavljevic
发明人： Mantu K. Hudait , Peter G. Tolchinsky , Jack T. Kavalieros , Marko Radosavljevic
IPC分类号： H01L29/205 , H01L21/268
CPC分类号： H01L21/02664 , H01L21/02381 , H01L21/02433 , H01L21/02461 , H01L21/02463 , H01L21/02532 , H01L21/02546 , H01L21/02549 , H01L21/02686 , H01L21/268
摘要： Dislocation removal from a group III-V film grown on a semiconductor substrate is generally described. In one example, an apparatus includes a semiconductor substrate, a buffer film including a group III-V semiconductor material epitaxially coupled to the semiconductor substrate wherein the buffer film includes material melted by laser pulse irradiation and recrystallized to substantially remove dislocations or defects from the buffer film, and a first semiconductor film epitaxially grown on the buffer film wherein a lattice mismatch exists between the semiconductor substrate and the first semiconductor film.
摘要翻译：通常描述从在半导体衬底上生长的III-V族膜脱离脱落。在一个示例中，一种装置包括半导体衬底，包括外延耦合到半导体衬底的III-V族半导体材料的缓冲膜，其中缓冲膜包括通过激光脉冲照射熔化的材料并重结晶以基本上从缓冲器中去除位错或缺陷膜，以及在所述缓冲膜上外延生长的第一半导体膜，其中在所述半导体衬底和所述第一半导体膜之间存在晶格失配。

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