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1. 发明申请

US20150001724A1 METHOD OF CREATING A MASKLESS AIR GAP IN BACK END INTERCONNECTS WITH DOUBLE SELF-ALIGNED VIAS 有权
标题翻译：在具有双重自对准VIAS的后端互连中创建无障碍空气隙的方法
公开(公告)号：US20150001724A1
公开(公告)日：2015-01-01
申请号：US13931219
申请日：2013-06-28
申请人： Manish CHANDHOK , Hui Jae Yoo , Yan A. Borodovsky , Florian Gstrein , David N. Shykind , Kevin L. Lin
发明人： Manish CHANDHOK , Hui Jae Yoo , Yan A. Borodovsky , Florian Gstrein , David N. Shykind , Kevin L. Lin
IPC分类号： H01L23/535 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/32133 , H01L21/32139 , H01L21/76802 , H01L21/7682 , H01L21/76877 , H01L21/76879 , H01L21/76883 , H01L21/76885 , H01L21/76886 , H01L21/76897 , H01L23/5222 , H01L23/528 , H01L23/53209 , H01L23/53271 , H01L23/5329 , H01L23/53295 , H01L23/535 , H01L2924/0002 , H01L2924/00
摘要： A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.
摘要翻译：一种方法，包括将互连材料的厚度尺寸图案化为具有从布线延伸的一个或多个通孔的布线的厚度尺寸，并将介电材料引入到互连材料上。一种包括将互连材料沉积和图案化成布线和一个或多个通孔的方法; 以及在所述互连材料上引入介电材料，使得所述一个或多个通孔通过所述介电材料暴露。一种装置，包括在第一平面中的第一互连层和在衬底上的第二平面中的第二互连; 以及分离所述第一和第二互连层的电介质层，其中所述第一互连层包括包括布线和至少一个通孔的整体，所述至少一个通孔从所述布线延伸到所述第二互连层的布线。

2. 发明授权

US08975138B2 Method of creating a maskless air gap in back end interconnects with double self-aligned vias 有权
标题翻译：在具有双自对准通孔的后端互连中产生无掩蔽气隙的方法
公开(公告)号：US08975138B2
公开(公告)日：2015-03-10
申请号：US13931219
申请日：2013-06-28
申请人： Manish Chandhok , Hui Jae Yoo , Yan A. Borodovsky , Florian Gstrein , David N. Shykind , Kevin L. Lin
发明人： Manish Chandhok , Hui Jae Yoo , Yan A. Borodovsky , Florian Gstrein , David N. Shykind , Kevin L. Lin
IPC分类号： H01L21/336 , H01L21/461 , H01L21/8234 , H01L23/535 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/32133 , H01L21/32139 , H01L21/76802 , H01L21/7682 , H01L21/76877 , H01L21/76879 , H01L21/76883 , H01L21/76885 , H01L21/76886 , H01L21/76897 , H01L23/5222 , H01L23/528 , H01L23/53209 , H01L23/53271 , H01L23/5329 , H01L23/53295 , H01L23/535 , H01L2924/0002 , H01L2924/00
摘要： A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.
摘要翻译：一种方法，包括将互连材料的厚度尺寸图案化为具有从布线延伸的一个或多个通孔的布线的厚度尺寸，并将介电材料引入到互连材料上。一种包括将互连材料沉积和图案化成布线和一个或多个通孔的方法; 以及在所述互连材料上引入介电材料，使得所述一个或多个通孔通过所述介电材料暴露。一种装置，包括在第一平面中的第一互连层和在衬底上的第二平面中的第二互连; 以及分离所述第一和第二互连层的电介质层，其中所述第一互连层包括包括布线和至少一个通孔的整体，所述至少一个通孔从所述布线延伸到所述第二互连层的布线。

3. 发明授权

US5532090A Method and apparatus for enhanced contact and via lithography 失效
标题翻译：用于增强接触和通过光刻的方法和装置
公开(公告)号：US5532090A
公开(公告)日：1996-07-02
申请号：US396961
申请日：1995-03-01
申请人： Yan A. Borodovsky
发明人： Yan A. Borodovsky
IPC分类号： G03F7/20 , G03F9/00
CPC分类号： G03F7/70283 , G03F7/2022 , G03F7/70466
摘要： An enhanced method and apparatus for forming openings in a photosensitive layer. Using a standard microlithographic printer such as stepper or scan and step system, an unpatterned photosensitive layer is exposed to a first mask having an opening pattern with dimensions within tight (for a given technology generation) process tolerances. Next, prior to development, the photosensitive layer is exposed to a second mask having a grid of clear spaces, surrounding the opening pattern. The combined exposure to the first and second mask forms a latent image of a reduced dimension opening. By the use of two exposures, with the exposure dose for each designed such that intensity profile is easily controllable in the presence of uncontrollable equipment imperfections and process variations, a reduced dimension opening can be formed in a highly manufacturable process with opening sizes smaller than that achievable through conventional lithographic techniques.
摘要翻译：一种用于在感光层中形成开口的增强方法和装置。使用诸如步进或扫描和步骤系统的标准微光刻打印机，将未图案化的感光层暴露于具有紧密尺寸（对于给定技术生成）工艺公差的开口图案的第一掩模。接下来，在显影之前，感光层暴露于围绕开口图案的具有透明空间格栅的第二掩模。与第一和第二掩模的组合曝光形成缩小尺寸开口的潜像。通过使用两次曝光，每个设计的曝光剂量使得强度分布在存在不可控制的设备缺陷和工艺变化的情况下易于控制，可以在高度可制造的工艺中形成尺寸小的开口，其开口尺寸小于可通过传统的光刻技术实现。

4. 发明授权

US5424154A Lithographic emhancement method and apparatus for randomly spaced structures 失效
标题翻译：用于随机间隔结构的平版印刷增强方法和装置
公开(公告)号：US5424154A
公开(公告)日：1995-06-13
申请号：US165395
申请日：1993-12-10
申请人： Yan A. Borodovsky
发明人： Yan A. Borodovsky
IPC分类号： G03F1/00 , G03F1/26 , G03F7/20 , G03F9/00
CPC分类号： G03F1/26 , G03F1/70 , G03F7/70125 , G03F7/70283
摘要： A method of enhancing the lithographic resolution of randomly laid out isolated structures is disclosed. A first mask comprises an active layer with isolated features such as gates. Portions of the active layer have a reduced dimension typical of periodic structures. The first mask additionally has complementary features provided along side the reduced active features to provide periodicity. In this way, the resolution of the lithographic process is enhanced, and other enhanced resolution technologies additionally can be used to best advantage to form a patterned photosensitive layer having isolated features of reduced width. The photosensitive layer is then exposed to a second mask which exposes the complementary features so that they are removed from the latent image in the photosensitive layer. This second exposure also further improves resolution by enhancing the contrast between exposed and unexposed regions. A method is disclosed for automatically providing random logic device layouts having the complementary features, as well as for providing a layout for the second mask.
摘要翻译：公开了一种增强随机铺设的隔离结构的光刻分辨率的方法。第一掩模包括具有诸如栅极的隔离特征的有源层。活性层的一部分具有典型的周期性结构的减小尺寸。第一个掩模还具有沿减少的主动特征提供的互补特征以提供周期性。以这种方式，增强了光刻工艺的分辨率，另外还可以使用其它增强分辨率技术来最大限度地利用形成具有减小的宽度的隔离特征的图案化感光层。然后将感光层暴露于暴露互补特征的第二掩模，使得它们从感光层中的潜像中去除。该第二曝光还通过增强曝光区域与未曝光区域之间的对比度进一步提高分辨率。公开了一种用于自动提供具有互补特征的随机逻辑设备布局以及为第二掩模提供布局的方法。

5. 发明授权

US4529685A Method for making integrated circuit devices using a layer of indium arsenide as an antireflective coating 失效
标题翻译：制造使用砷化铟层作为抗反射涂层的集成电路器件的方法
公开(公告)号：US4529685A
公开(公告)日：1985-07-16
申请号：US585808
申请日：1984-03-02
申请人： Yan A. Borodovsky
发明人： Yan A. Borodovsky
IPC分类号： G03C1/00 , G02B1/10 , G03F7/09 , G03F7/11 , H01L21/027 , H01L21/30 , H01L21/314 , G03C5/00
CPC分类号： H01L21/314 , G03F7/091 , H01L21/0274 , H01L21/0276
摘要： An improved method for making an integrated circuit device is disclosed which comprises coating a reflective layer with an antireflective coating comprising a layer of indium arsenide before applying a layer of photosensitive material or photoresist during production of the device. Light passing through the photosensitive material is absorbed by the antireflective coating so that only the minor amount of light required for alignment is reflected back through the photosensitive material resulting in sharper pattern definition in the photoresistive material and better process control overall. The antireflective indium arsenide layer is applied in a thickness of at least 500 angstroms and is further characterized by an 10 to 25% reflectivity relatively independent of coating thickness and wave length of light in the frequency range normally used to expose photoresist material.
摘要翻译：公开了一种用于制造集成电路器件的改进方法，其包括在制造器件之前施加一层感光材料或光致抗蚀剂之前，用包括砷化铟层的抗反射涂层涂覆反射层。通过感光材料的光被抗反射涂层吸收，使得只有少量的对准所需的光通过感光材料反射回来，导致光致抗蚀剂材料中更清晰的图案定义和更好的工艺控制。抗反射铟砷化物层以至少500埃的厚度施加，并且进一步的特征在于在通常用于曝光光致抗蚀剂材料的频率范围内相对独立于涂层厚度和光波长的10至25％的反射率。

6. 发明授权

US4580332A Forming a conductive, protective layer for multilayer metallization 失效
标题翻译：形成用于多层金属化的导电保护层
公开(公告)号：US4580332A
公开(公告)日：1986-04-08
申请号：US593335
申请日：1984-03-26
申请人： Yan A. Borodovsky
发明人： Yan A. Borodovsky
IPC分类号： H01L21/768 , H01L23/532 , H01L21/58
CPC分类号： H01L21/76886 , H01L23/53271 , H01L2924/0002 , Y10S438/945 , Y10S438/968 , Y10S438/97
摘要： An improved integrated circuit structure, and method of making the structure, is disclosed wherein at least one metallization layer is coated with a conductive indium arsenide layer during production of the structure and an upper metallization layer subsequently is applied to the structure wherein at least a portion of the subsequent metallization layer is in ohmic contact with the conductive indium arsenide layer whereby the lower metallization layer is protected by the intervening indium arsenide layer during subsequent removal of the upper metallization layer if subsequent reworking of the structure becomes necessary. The use of the indium arsenide layer over a metallization layer further enhances the construction process by the use of its antireflective properties during patterning of a photoresist applied over the indium arsenide layer.
摘要翻译：公开了一种改进的集成电路结构和制造该结构的方法，其中至少一个金属化层在该结构的制造期间被导电的砷化铟层涂覆，并且上部金属化层随后被施加到该结构，其中至少一部分随后的金属化层与导电铟砷化物层欧姆接触，由此如果随后的结构的再加工变得必要，则随后去除上部金属化层期间，下部金属化层被中间的砷化铟层保护。在金属化层上使用砷化铟层通过在对砷化铟层施加的光刻胶进行图案化期间通过使用其抗反射特性进一步增强了施工过程。

7. 发明授权

US5498579A Method of producing semiconductor device layer layout 失效
标题翻译：制造半导体器件层布局的方法
公开(公告)号：US5498579A
公开(公告)日：1996-03-12
申请号：US255655
申请日：1994-06-08
申请人： Yan A. Borodovsky , Ananda G. Sarangi
发明人： Yan A. Borodovsky , Ananda G. Sarangi
IPC分类号： G03F1/00 , G03F1/26 , G03F7/20 , H01L21/00
CPC分类号： G03F1/26 , G03F1/70 , G03F7/70125 , G03F7/70283
摘要： A method of enhancing the lithographic resolution of randomly laid out isolated structures is disclosed. A first mask comprises an active layer with isolated features such as gates. Portions of the active layer have a reduced dimension typical of periodic structures. The first mask additionally has complementary features provided along side the reduced active features to provide periodicity. In this way, the resolution of the lithographic process is enhanced, and other enhanced resolution technologies additionally can be used to best advantage to form a patterned photosensitive layer having isolated features of reduced width. The photosensitive layer is then exposed to a second mask which exposes the complementary features so that they are removed from the latent image in the photosensitive layer. This second exposure also further improves resolution by enhancing the contrast between exposed and unexposed regions. A method is disclosed for automatically providing random logic device layouts having the complementary features, as well as for providing a layout for the second mask.
摘要翻译：公开了一种增强随机铺设的隔离结构的光刻分辨率的方法。第一掩模包括具有诸如栅极的隔离特征的有源层。活性层的一部分具有典型的周期性结构的减小尺寸。第一个掩模还具有沿减少的主动特征提供的互补特征以提供周期性。以这种方式，增强了光刻工艺的分辨率，另外还可以使用其它增强分辨率技术来最大限度地利用形成具有减小的宽度的隔离特征的图案化感光层。然后将感光层暴露于暴露互补特征的第二掩模，使得它们从感光层中的潜像中去除。该第二曝光还通过增强曝光区域与未曝光区域之间的对比度进一步提高分辨率。公开了一种用于自动提供具有互补特征的随机逻辑设备布局以及为第二掩模提供布局的方法。

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