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1. 发明申请

US20090200767A1 APPARATUS FOR MOUNTING STABILIZER BAR FOR VEHICLES 审中-公开
标题翻译：用于安装车辆稳定杆的装置
公开(公告)号：US20090200767A1
公开(公告)日：2009-08-13
申请号：US12306400
申请日：2007-01-08
申请人： Man-Seung Lim , Jin-Young Kim , Yung-Jin Kang
发明人： Man-Seung Lim , Jin-Young Kim , Yung-Jin Kang
IPC分类号： B60G21/055
CPC分类号： F16F1/38 , B60G21/0551 , B60G2204/1222 , B60G2204/41
摘要： An apparatus for mounting a stabilizer bar to a vehicle body frame is disclosed. The stabilizer bar mounting apparatus (1) of the present invention includes a rubber bushing (10), metal plates (30) and a mounting bracket (20). The rubber bushing (10) includes a main body (100), which has a holding hole (100a) for insertion of the stabilizer bar (2), and has a slit (100b) extending from an upper surface thereof to the holding hole (100a). Elastic holes (101) are formed in each of the opposite ends of the main body (100) to reduce stiffness of the main body in a rotational direction. The metal plates (30) are inserted into the main body of the rubber bushing (10) to prevent the rubber bushing from being deformed. The mounting bracket (20) includes a bushing receiving part (200) and a pair of mounting plates (201), which are provided on respective opposite edges of the bushing receiving part, so that the mounting bracket receives and fastens the rubber bushing to the vehicle body frame.
摘要翻译：公开了一种用于将稳定杆安装在车体框架上的装置。本发明的稳定杆安装装置（1）包括橡胶衬套（10），金属板（30）和安装托架（20）。橡胶衬套（10）包括主体（100），其具有用于插入稳定杆（2）的保持孔（100a），并且具有从其上表面延伸到保持孔的狭缝（100b） 100a）。弹性孔（101）形成在主体（100）的每个相对端中，以降低主体在旋转方向上的刚度。金属板（30）插入橡胶衬套（10）的主体中，以防止橡胶衬套变形。安装支架（20）包括衬套接收部分（200）和一对安装板（201），它们设置在衬套接收部分的相对的相对边缘上，使得安装支架接收和紧固橡胶衬套车体框架

2. 发明授权

US09094482B2 Apparatus and method for controlling data transmission/reception path between server and mobile terminal in heterogeneous network environment 有权
标题翻译：用于控制异构网络环境中服务器与移动终端之间的数据发送/接收路径的装置和方法
公开(公告)号：US09094482B2
公开(公告)日：2015-07-28
申请号：US13484401
申请日：2012-05-31
申请人： Jin-Young Kim , Young-Sam Jun
发明人： Jin-Young Kim , Young-Sam Jun
IPC分类号： H04W8/26 , H04W36/14 , H04L29/12
CPC分类号： H04L61/6077 , H04L61/2528 , H04L61/2553 , H04W8/26 , H04W36/14
摘要： A data transmission/reception path between a server and a mobile terminal in a heterogeneous network environment is controlled by mapping at least one actual Internet protocol (IP) address available to the mobile terminal in the heterogeneous network environment to at least one virtual IP to generate a path mapping table, and determining a data transmission/reception path between the server and the mobile terminal with reference to the generated path mapping table. This virtualization of terminal actual addresses with respect to a server improves service continuity in an efficient, low cost manner, independent of the need to modify the OS kernel in various devices.
摘要翻译：通过将异构网络环境中的移动终端可用的至少一个实际因特网协议（IP）地址映射到至少一个虚拟IP来生成异构网络环境中的服务器和移动终端之间的数据发送/接收路径，以产生路径映射表，并且参考生成的路径映射表来确定服务器与移动终端之间的数据发送/接收路径。终端实际地址相对于服务器的这种虚拟化可以以有效，低成本的方式提高服务连续性，而与在各种设备中修改OS内核的需要无关。

3. 发明授权

US08901645B2 Semiconductor devices including bit line contact plug and peripheral transitor 有权
标题翻译：半导体器件包括位线接触插头和外设过渡器
公开(公告)号：US08901645B2
公开(公告)日：2014-12-02
申请号：US13864347
申请日：2013-04-17
申请人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
发明人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
IPC分类号： H01L29/66 , H01L29/78 , H01L29/423 , H01L27/108
CPC分类号： H01L23/528 , H01L23/535 , H01L27/1052 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L29/0649 , H01L29/42324 , H01L29/45 , H01L29/78 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.
摘要翻译：具有单元区域和周边区域的半导体器件包括半导体基板，限定单元区域中的半导体基板的单元有源区域的单元绝缘隔离区域，设置在单元区域中的半导体基板内的字线，位设置在单元有源区上的线接触插塞，位线接触插头上的位线，限定周边区域中的半导体衬底的周边有源区域的外围绝缘隔离区域以及包括周边晶体管下电极的外围晶体管和周边晶体管上电极。位线接触插塞形成在半导体器件中与外围晶体管下电极相同的电平上，并且位线电极在半导体器件中形成为与外围晶体管上电极相同的电平。

4. 发明授权

US08626125B2 Apparatus and method for securing mobile terminal 有权
标题翻译：用于固定移动终端的装置和方法
公开(公告)号：US08626125B2
公开(公告)日：2014-01-07
申请号：US13351119
申请日：2012-01-16
申请人： Joon-Seub Lee , Jin-Young Kim , Min-Che Jeong
发明人： Joon-Seub Lee , Jin-Young Kim , Min-Che Jeong
IPC分类号： H04M1/66
CPC分类号： G06F21/45 , G06F21/52 , G06F21/554
摘要： A mobile terminal and a method for securing information are provided. The mobile terminal includes an application part to receive information related to an application; a determining unit to receive a command issued by the application and to determine whether the command or the application is authorized to access a system resource of the mobile terminal; and a blocking unit to block an execution of the command in response to a determination that the execution of the command is unauthorized or issued by the unauthorized application. The method includes receiving information related to an application; receiving a request for executing a command issued by the application; determining whether the requested command or the application is authorized to access a system resource of a mobile terminal; and blocking execution of the command in response to a determination that the execution of the command is unauthorized or issued by an unauthorized application.
摘要翻译：提供了移动终端和用于保护信息的方法。移动终端包括用于接收与应用有关的信息的应用部分; 确定单元，用于接收由所述应用发出的命令并确定所述命令或所述应用是否被授权访问所述移动终端的系统资源; 以及阻塞单元，用于响应于所述命令的执行被未经授权的应用未经授权或发出的确定而阻止所述命令的执行。该方法包括接收与应用有关的信息; 接收执行应用程序发出的命令的请求; 确定所请求的命令或应用程序是否被授权访问移动终端的系统资源; 以及响应于所述命令的执行被未授权或未被授权的应用发出的确定而阻止所述命令的执行。

5. 发明申请

US20130228856A1 SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND PERIPHERAL TRANSISTOR 有权
公开(公告)号：US20130228856A1
公开(公告)日：2013-09-05
申请号：US13864347
申请日：2013-04-17
申请人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
发明人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
IPC分类号： H01L29/78
CPC分类号： H01L23/528 , H01L23/535 , H01L27/1052 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L29/0649 , H01L29/42324 , H01L29/45 , H01L29/78 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

6. 发明授权

US08199592B2 Semiconductor memory devices with mismatch cells 有权
标题翻译：具有不匹配单元的半导体存储器件
公开(公告)号：US08199592B2
公开(公告)日：2012-06-12
申请号：US12591196
申请日：2009-11-12
申请人： Jin-Young Kim , Chul-Woo Park , Ki-Whan Song
发明人： Jin-Young Kim , Chul-Woo Park , Ki-Whan Song
IPC分类号： G11C7/00
CPC分类号： G11C11/4099 , G11C11/4091
摘要： A semiconductor memory device having the mismatch cell makes a capacitance difference between a bit line pair relatively large during a read operation using at least one dummy memory cell as a mismatch cell selected together with a corresponding memory cell. Therefore, data of a semiconductor memory device may be detected more easily.
摘要翻译：具有不匹配单元的半导体存储器件在使用至少一个虚拟存储器单元作为与对应的存储器单元一起选择的不匹配单元的读取操作期间，位线对之间的电容差相对较大。因此，可以更容易地检测半导体存储器件的数据。

7. 发明申请

US20110305069A1 NONVOLATILE MEMORY DEVICE USING RESISTANCE MATERIAL AND MEMORY SYSTEM INCLUDING THE NONVOLATILE MEMORY DEVICE 有权
标题翻译：使用电阻材料和包含非易失性存储器件的存储器系统的非易失性存储器件
公开(公告)号：US20110305069A1
公开(公告)日：2011-12-15
申请号：US13155492
申请日：2011-06-08
申请人： Jin-Young Kim , Ki-Whan Song
发明人： Jin-Young Kim , Ki-Whan Song
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C7/18 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0038
摘要： A nonvolatile memory device includes: a memory array including a plurality of memory banks which are arranged in a first direction; a write global bit line and a read global bit line extending in the first direction to be shared by the memory banks; a write circuit connected to the write global bit line and disposed on a first side of the memory array; and a read circuit connected to the read global bit line and disposed on a second side of the memory array opposite the first side of the memory array, wherein each of the memory banks extends in a second direction different from the first direction and comprises a plurality of nonvolatile memory cells, each of the nonvolatile memory cells having a variable resistive element whose resistance value varies according to data stored therein.
摘要翻译：非易失性存储器件包括：存储器阵列，包括沿第一方向布置的多个存储体; 写入全局位线和在第一方向上延伸以由存储体共享的读取全局位线; 写入电路，连接到写入全局位线并且设置在存储器阵列的第一侧上; 以及读取电路，连接到读取的全局位线并且设置在与存储器阵列的第一侧相对的存储器阵列的第二侧上，其中每个存储体沿与第一方向不同的第二方向延伸并且包括多个的非易失性存储单元，每个非易失性存储单元具有可变电阻元件，其电阻值根据存储在其中的数据而变化。

8. 发明申请

US20100124135A1 Semiconductor memory devices having hierarchical bit-line structures 有权
标题翻译：具有分层位线结构的半导体存储器件
公开(公告)号：US20100124135A1
公开(公告)日：2010-05-20
申请号：US12591254
申请日：2009-11-13
申请人： Jin-Young Kim , Ki-Whan Song
发明人： Jin-Young Kim , Ki-Whan Song
IPC分类号： G11C16/06
CPC分类号： G11C11/4091 , G11C11/4097 , G11C2207/002
摘要： The semiconductor memory device includes a memory cell array and a switching circuit. The memory cell array includes a plurality of first memory cells connected between word lines and first local bit lines, and a plurality of second memory cells connected between the word lines and second local bit lines. The switching circuit is configured to respectively connect the first local bit lines to first global bit lines during a first sensing period, and to respectively connect the second local bit lines to second global bit lines during a second sensing period of a reading operation. The semiconductor memory device further includes a sensing circuit configured to sense and amplify data from the first global bit lines during the first sensing period, and to sense and amplify data from the second global bit lines during the second sensing period of the reading operation.
摘要翻译：半导体存储器件包括存储单元阵列和开关电路。存储单元阵列包括连接在字线和第一局部位线之间的多个第一存储单元，以及连接在字线和第二局部位线之间的多个第二存储单元。开关电路被配置为在第一感测周期期间将第一本地位线分别连接到第一全局位线，并且在读取操作的第二感测周期期间将第二局部位线分别连接到第二全局位线。半导体存储器件还包括感测电路，其被配置为在第一感测周期期间感测和放大来自第一全局位线的数据，并且在读取操作的第二感测周期期间感测和放大来自第二全局位线的数据。

9. 发明申请

US20080151665A1 Semiconductor integrated circuit and method of operating the same 失效
标题翻译：半导体集成电路及其操作的方法
公开(公告)号：US20080151665A1
公开(公告)日：2008-06-26
申请号：US11882931
申请日：2007-08-07
申请人： Jin-Young Kim , Ki-Whan Song , Duk-Ha Park
发明人： Jin-Young Kim , Ki-Whan Song , Duk-Ha Park
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C11/4096 , G11C2207/002 , G11C2207/005 , G11C2211/4016
摘要： One embodiment includes a plurality of word lines, a plurality of bit lines intersecting with the plurality of word lines, a plurality of memory cells formed at intersections of and connected to the plurality of word lines and the plurality of bit lines. Each of the plurality of memory cells may be a floating body cell. A bit line selecting circuit may be configured to selectively connect each of the plurality of bit lines to an output bit line. The embodiment may further include plurality of sense amplifiers, where the plurality of sense amplifiers is greater than one and less than the plurality of bit lines in number. A sense amplifier switching structure may be configured to selectively connect each of the plurality of sense amplifiers to the output bit line.
摘要翻译：一个实施例包括多个字线，与多个字线相交的多个位线，多个存储单元，形成在多个字线和多个位线的交叉点处并与之连接。多个存储单元中的每一个可以是浮动体单元。位线选择电路可以被配置为选择性地将多个位线中的每一个连接到输出位线。该实施例还可以包括多个读出放大器，其中多个读出放大器的数量大于一个且小于多个位线。读出放大器切换结构可以被配置为选择性地将多个读出放大器中的每一个连接到输出位线。

10. 发明申请

US20070252196A1 Vertical channel transistors and memory devices including vertical channel transistors 失效
标题翻译：垂直沟道晶体管和包括垂直沟道晶体管的存储器件
公开(公告)号：US20070252196A1
公开(公告)日：2007-11-01
申请号：US11801915
申请日：2007-02-08
申请人： Jin-Young Kim , Ki-Whan Song
发明人： Jin-Young Kim , Ki-Whan Song
IPC分类号： H01L27/092 , H01L29/78 , H01L31/00 , H01L29/94
CPC分类号： H01L21/823842 , H01L21/823885 , H01L27/092 , H01L27/105 , H01L27/1052
摘要： A semiconductor device is provided which includes an NMOS vertical channel transistor located on a substrate and including a p+ polysilicon gate electrode surrounding a vertical p-channel region, and a PMOS vertical channel transistor located on the substrate and including an n+ polysilicon gate electrode surrounding a vertical n-channel region. The NMOS and PMOS vertical channel transistors are optionally operable in a CMOS operational mode.
摘要翻译：提供了一种半导体器件，其包括位于衬底上并包括围绕垂直p沟道区的p +多晶硅栅电极的NMOS垂直沟道晶体管和位于衬底上的PMOS垂直沟道晶体管，并且包括n + 垂直n沟道区域。 NMOS和PMOS垂直沟道晶体管可选地以CMOS操作模式工作。

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