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1. 发明授权

US5453788A Apparatus for converting encoded data into image data, including data preparing circuit, to allow enlargement or reduction of image 失效
标题翻译：用于将编码数据转换为图像数据的装置，包括用于在逆DCT变换之前增加或删除DCT系数数据块的高频部分中的DCT系数数据的数据准备电路，以允许放大或缩小图像
公开(公告)号：US5453788A
公开(公告)日：1995-09-26
申请号：US194179
申请日：1994-02-09
申请人： Makoto Matsushima , Ryo Fukui
发明人： Makoto Matsushima , Ryo Fukui
IPC分类号： H03M7/30 , G06T3/40 , G06T9/00 , H04N1/41 , H04N5/262 , H04N7/12 , H04N19/132 , H04N19/162 , H04N19/42 , H04N19/48 , H04N19/60 , H04N19/625 , H04N19/91
CPC分类号： H04N5/2628 , G06T3/4084 , H04N19/176 , H04N19/18 , H04N19/48 , H04N19/527 , H04N19/59 , H04N19/86 , H04N19/90 , H04N7/12 , H04N19/124 , H04N19/132 , H04N19/60
摘要： An image processing apparatus includes: a first transforming device for transforming encoded data into discrete cosine transform coefficient data segmented into processing blocks, each block being formed of a matrix of m.times.n pixels; and a setting device for setting the values of M and N defining the size of a matrix forming each processing block used in inverse discrete cosine transform. The image processing apparatus also includes a data preparing circuit for adding discrete cosine transform coefficient data to, or deleting discrete cosine transform coefficient data from, a high-frequency domain of the discrete cosine transform coefficient data and segmented into processing blocks, each block being formed of a matrix of m.times.n pixels, and for preparing discrete cosine transform coefficient data segmented into processing blocks, each block being formed of a matrix of M.times.N pixels; a second transforming device for subjecting the discrete cosine transform coefficient data prepared by the data preparing circuit to inverse discrete cosine transform, so that image data can be output; and an outputting device for outputting image data output from the second transforming device and segmented into processing blocks as continuous image data.
摘要翻译：一种图像处理装置包括：第一变换装置，用于将编码数据变换成分割成处理块的离散余弦变换系数数据，每个块由m×n个像素的矩阵形成; 以及设定装置，用于设定定义形成用于逆离散余弦变换的每个处理块的矩阵的大小的M和N的值。该图像处理装置还包括数据准备电路，用于将离散余弦变换系数数据加到离散余弦变换系数数据的高频域中，或者从其离散余弦变换系数数据中删除离散余弦变换系数数据，并将其分割成处理块，形成每个块的m×n像素的矩阵，并且用于准备分割成处理块的离散余弦变换系数数据，每个块由M×N个像素的矩阵形成; 第二变换装置，用于对由数据准备电路准备的离散余弦变换系数数据进行逆离散余弦变换，从而可以输出图像数据; 以及输出装置，用于输出从第二变换装置输出并被分割成处理块的图像数据作为连续图像数据。

2. 发明申请

US20080203933A1 PULSE WIDTH MODULATION SIGNAL GENERATING CIRCUIT 有权
标题翻译：脉冲宽度调制信号发生电路
公开(公告)号：US20080203933A1
公开(公告)日：2008-08-28
申请号：US12061360
申请日：2008-04-02
申请人： Makoto Matsushima
发明人： Makoto Matsushima
IPC分类号： H05B37/02 , H03K7/08
CPC分类号： H05B33/0818 , H03K7/08 , H05B33/0848 , Y02B20/346
摘要： A PWM signal generating circuit outputs a stable PWM signal for increasing and deceasing a duty ratio at a predetermined rate within a predetermined period without requiring an improvement of a process capacity of a CPU as compared to a conventional PWM signal generating circuit. The PWM signal generating circuit consists of a plurality of circuit elements each of which outputs a digital signal. A first counter circuit periodically changes a PWM signal output therefrom into an active state. A second counter circuit changes the PWM signal, which has been changed into the active state by the first counter circuit, into an inactive state within each cycle. The second counter circuit increases and decreases an active-to-inactive time period from a time when the PWM signal is changed into the active state to a time when the PWM signal is changed into the inactive state.
摘要翻译： PWM信号发生电路输出稳定的PWM信号，用于在预定时间段内以预定速率增加和减少占空比，而不需要改进CPU的处理能力，而不是传统的PWM信号发生电路。 PWM信号产生电路由多个电路元件组成，每个电路元件输出数字信号。第一计数器电路将从其输出的PWM信号周期性地改变为活动状态。第二计数器电路将已经被第一计数器电路改变为活动状态的PWM信号在每个周期内变为非活动状态。第二计数器电路从PWM信号变为有效状态的时刻到PWM信号变为不活动状态的时刻，增加和减少从有源到非活动时间段。

3. 发明申请

US20080272759A1 DC converter with halt mode setting means 失效
公开(公告)号：US20080272759A1
公开(公告)日：2008-11-06
申请号：US12216221
申请日：2008-07-01
申请人： Katsuhiko Manabe , Tomonari Katoh , Minoru Sugiyama , Makoto Matsushima , Tadayoshi Ueda
发明人： Katsuhiko Manabe , Tomonari Katoh , Minoru Sugiyama , Makoto Matsushima , Tadayoshi Ueda
IPC分类号： G05F1/56
CPC分类号： H02M1/32 , H02M3/156 , H02M2001/0032 , Y02B70/16
摘要： A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

4. 发明申请

US20060125459A1 DC converter with halt mode setting means 有权
标题翻译： DC转换器，具有停止模式设置装置
公开(公告)号：US20060125459A1
公开(公告)日：2006-06-15
申请号：US11350742
申请日：2006-02-10
申请人： Katsuhiko Manabe , Tomonari Katoh , Minoru Sugiyama , Makoto Matsushima , Tadayoshi Ueda
发明人： Katsuhiko Manabe , Tomonari Katoh , Minoru Sugiyama , Makoto Matsushima , Tadayoshi Ueda
IPC分类号： G05F1/40 , G05F1/56
CPC分类号： H02M1/32 , H02M3/156 , H02M2001/0032 , Y02B70/16
摘要： A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.
摘要翻译：公开了一种具有停止模式设置的DC转换器，用于防止过电流的发生，同时减轻电路尺寸的增加，以及用于设置这种停止模式的方法。 DC转换器包括半导体开关，时钟发生器，用于向半导体开关的栅极输出时钟信号，以用于控制半导体开关的接通/关断时间，使得从发电机输出预定功率;以及驱动电路，用于根据暂停模式设定要求将半导体开关切换到连续导通状态，无论时钟信号如何，当半导体开关通常重复响应时钟信号的开/关操作处于其截止状态时。

5. 发明授权

US07701187B2 DC converter with halt mode setting means 失效
标题翻译： DC转换器，具有停止模式设置装置
公开(公告)号：US07701187B2
公开(公告)日：2010-04-20
申请号：US12216221
申请日：2008-07-01
申请人： Katsuhiko Manabe , Tomonari Katoh , Minoru Sugiyama , Makoto Matsushima , Tadayoshi Ueda
发明人： Katsuhiko Manabe , Tomonari Katoh , Minoru Sugiyama , Makoto Matsushima , Tadayoshi Ueda
IPC分类号： G05F1/56
CPC分类号： H02M1/32 , H02M3/156 , H02M2001/0032 , Y02B70/16
摘要： A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.
摘要翻译：公开了一种具有停止模式设置的DC转换器，用于防止过电流的发生，同时减轻电路尺寸的增加，以及用于设置这种停止模式的方法。 DC转换器包括半导体开关，时钟发生器，用于向半导体开关的栅极输出时钟信号，以用于控制半导体开关的接通/关断时间，使得从发电机输出预定功率;以及驱动电路，用于根据暂停模式设定要求将半导体开关切换到连续导通状态，无论时钟信号如何，当半导体开关通常重复响应时钟信号的开/关操作处于其截止状态时。

6. 发明申请

US20080197872A1 SEMICONDUCTOR CHIP, MULTI-CHIP SEMICONDUCTOR DEVICE, INSPECTION METHOD OF THE SAME, AND ELECTRIC APPLIANCE INTEGRATING THE SAME 审中-公开
标题翻译：半导体芯片，多芯片半导体器件，其检测方法及其电器整合
公开(公告)号：US20080197872A1
公开(公告)日：2008-08-21
申请号：US12014472
申请日：2008-01-15
申请人： Makoto Matsushima
发明人： Makoto Matsushima
IPC分类号： G01R31/27 , H01L23/482
CPC分类号： G01R31/2853 , G01R31/2884 , H01L25/0655 , H01L25/0657 , H01L2224/05553 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/48235 , H01L2224/48464 , H01L2224/49175 , H01L2225/06596 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A disclosed semiconductor chip includes a first connection pad adapted to input an input signal; and a second connection pad adapted to selectively output, according to a test mode signal input to the semiconductor chip, one of the input signal and an output signal from the semiconductor chip.
摘要翻译：所公开的半导体芯片包括适于输入输入信号的第一连接焊盘; 以及第二连接焊盘，其适于根据输入到所述半导体芯片的测试模式信号选择性地输出所述输入信号中的一个和来自所述半导体芯片的输出信号。

7. 发明授权

US07193400B2 DC converter with halt mode setting means 有权
公开(公告)号：US07193400B2
公开(公告)日：2007-03-20
申请号：US11350742
申请日：2006-02-10
申请人： Katsuhiko Manabe , Tomonari Katoh , Minoru Sugiyama , Makoto Matsushima , Tadayoshi Ueda
发明人： Katsuhiko Manabe , Tomonari Katoh , Minoru Sugiyama , Makoto Matsushima , Tadayoshi Ueda
IPC分类号： G05F1/56
CPC分类号： H02M1/32 , H02M3/156 , H02M2001/0032 , Y02B70/16
摘要： A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

8. 发明授权

US07953145B2 Pulse width modulation signal generating circuit 有权
标题翻译：脉宽调制信号发生电路
公开(公告)号：US07953145B2
公开(公告)日：2011-05-31
申请号：US12061360
申请日：2008-04-02
申请人： Makoto Matsushima
发明人： Makoto Matsushima
IPC分类号： H03K7/08 , H03K9/08
CPC分类号： H05B33/0818 , H03K7/08 , H05B33/0848 , Y02B20/346
摘要： A PWM signal generating circuit outputs a stable PWM signal for increasing and decreasing a duty ratio at a predetermined rate within a predetermined period without requiring an improvement of a process capacity of a CPU as compared to a conventional PWM signal generating circuit. The PWM signal generating circuit consists of a plurality of circuit elements each of which outputs a digital signal. A first counter circuit periodically changes a PWM signal output therefrom into an active state. A second counter circuit changes the PWM signal, which has been changed into the active state by the first counter circuit, into an inactive state within each cycle. The second counter circuit increases and decreases an active-to-inactive time period from a time when the PWM signal is changed into the active state to a time when the PWM signal is changed into the inactive state.
摘要翻译： PWM信号发生电路输出用于在预定时间内以预定速率增加和减小占空比的稳定PWM信号，而不需要改善CPU的处理能力，而不是传统的PWM信号发生电路。 PWM信号产生电路由多个电路元件组成，每个电路元件输出数字信号。第一计数器电路将从其输出的PWM信号周期性地改变为活动状态。第二计数器电路将已经被第一计数器电路改变为活动状态的PWM信号在每个周期内变为非活动状态。第二计数器电路从PWM信号变为有效状态的时刻到PWM信号变为不活动状态的时刻，增加和减少从有源到非活动时间段。

9. 发明授权

US07408334B2 DC converter with halt mode setting means 失效
标题翻译： DC转换器，具有停止模式设置装置
公开(公告)号：US07408334B2
公开(公告)日：2008-08-05
申请号：US11705584
申请日：2007-02-13
申请人： Katsuhiko Manabe , Tomonari Katoh , Minoru Sugiyama , Makoto Matsushima , Tadayoshi Ueda
发明人： Katsuhiko Manabe , Tomonari Katoh , Minoru Sugiyama , Makoto Matsushima , Tadayoshi Ueda
IPC分类号： G05F1/56
CPC分类号： H02M1/32 , H02M3/156 , H02M2001/0032 , Y02B70/16
摘要： A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.
摘要翻译：公开了一种具有停止模式设置的DC转换器，用于防止过电流的发生，同时减轻电路尺寸的增加，以及用于设置这种停止模式的方法。 DC转换器包括半导体开关，时钟发生器，用于向半导体开关的栅极输出时钟信号，以用于控制半导体开关的接通/关断时间，使得从发电机输出预定功率;以及驱动电路，用于根据暂停模式设定要求将半导体开关切换到连续导通状态，无论时钟信号如何，当半导体开关通常重复响应时钟信号的开/关操作处于其截止状态时。

10. 发明授权

US07372902B2 Pulse with modulation signal generating circuit 失效
标题翻译：具有调制信号发生电路的脉冲
公开(公告)号：US07372902B2
公开(公告)日：2008-05-13
申请号：US10695839
申请日：2003-10-29
申请人： Makoto Matsushima
发明人： Makoto Matsushima
IPC分类号： H03K7/08 , H03K9/08
CPC分类号： H05B33/0818 , H03K7/08 , H05B33/0848 , Y02B20/346
摘要： A PWM signal generating circuit outputs a stable PWM signal for increasing and deceasing a duty ratio at a predetermined rate within a predetermined period without requiring an improvement of a process capacity of a CPU as compared to a conventional PWM signal generating circuit. The PWM signal generating circuit consists of a plurality of circuit elements each of which outputs a digital signal. A first counter circuit periodically changes a PWM signal output therefrom into an active state. A second counter circuit changes the PWM signal, which has been changed into the active state by the first counter circuit, into an inactive state within each cycle. The second counter circuit increases and decreases an active-to-inactive time period from a time when the PWM signal is changed into the active state to a time when the PWM signal is changed into the inactive state.
摘要翻译： PWM信号发生电路输出稳定的PWM信号，用于在预定时间段内以预定速率增加和减少占空比，而不需要改进CPU的处理能力，而不是传统的PWM信号发生电路。 PWM信号产生电路由多个电路元件组成，每个电路元件输出数字信号。第一计数器电路将从其输出的PWM信号周期性地改变为活动状态。第二计数器电路将已经被第一计数器电路改变为活动状态的PWM信号在每个周期内变为非活动状态。第二计数器电路从PWM信号变为有效状态的时刻到PWM信号变为不活动状态的时刻，增加和减少从有源到非活动时间段。

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