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1. 发明授权

US08094491B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08094491B2
公开(公告)日：2012-01-10
申请号：US12230283
申请日：2008-08-27
申请人： Makoto Kitagawa , Mitsuo Soneda
发明人： Makoto Kitagawa , Mitsuo Soneda
IPC分类号： G11C11/39
CPC分类号： G11C11/39
摘要： A semiconductor device includes a memory cell including a thyristor element with a gate having a pnpn structure formed in a semiconductor substrate, and a plurality of access transistors formed on the semiconductor substrate and each connected at a first terminal thereof to a storage node at one terminal of the thyristor element such that a potential at the storage node can be transmitted to bit lines different from each other, the gate of the thyristor element and the gates of the plurality of access transistors of the memory cell being connected to word lines different from one another.
摘要翻译：一种半导体器件包括：存储单元，具有在半导体衬底中形成有pnpn结构的栅极的晶闸管元件和形成在半导体衬底上并分别在其第一端部连接到一个端子处的存储节点的多个存取晶体管的晶闸管元件，使得存储节点处的电位可以传输到彼此不同的位线，晶闸管元件的栅极和存储单元的多个存取晶体管的栅极连接到不同于一个的字线另一个。

2. 发明申请

US20090086536A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20090086536A1
公开(公告)日：2009-04-02
申请号：US12230283
申请日：2008-08-27
申请人： Makoto Kitagawa , Mitsuo Soneda
发明人： Makoto Kitagawa , Mitsuo Soneda
IPC分类号： G11C11/34 , G11C7/00 , G11C8/00
CPC分类号： G11C11/39
摘要： A semiconductor device includes a memory cell including a thyristor element with a gate having a pnpn structure formed in a semiconductor substrate, and a plurality of access transistors formed on the semiconductor substrate and each connected at a first terminal thereof to a storage node at one terminal of the thyristor element such that a potential at the storage node can be transmitted to bit lines different from each other, the gate of the thyristor element and the gates of the plurality of access transistors of the memory cell being connected to word lines different from one another.
摘要翻译：一种半导体器件包括：存储单元，具有在半导体衬底中形成有pnpn结构的栅极的晶闸管元件和形成在半导体衬底上并分别在其第一端部连接到一个端子处的存储节点的多个存取晶体管的晶闸管元件，使得存储节点处的电位可以传输到彼此不同的位线，晶闸管元件的栅极和存储单元的多个存取晶体管的栅极连接到不同于一个的字线另一个。

3. 发明授权

US5914631A Voltage generating circuit 失效
标题翻译：电压发生电路
公开(公告)号：US5914631A
公开(公告)日：1999-06-22
申请号：US905563
申请日：1997-08-04
申请人： Mitsuo Soneda
发明人： Mitsuo Soneda
IPC分类号： G05F3/24 , G05F1/46 , G05F1/56 , G11C11/407 , H03L7/06 , G05F1/10
CPC分类号： G05F1/465
摘要： A voltage controlled delay circuit is formed by m number of gates connected in series, phases of a clock signal and a delay signal are compared by a phase comparator, an up signal or a down signal is output, an integrated signal is generated by an integrator, a voltage signal following this is generated by a buffer and fed back as an operating power source voltage to the voltage controlled delay circuit, and further an internal power source voltage following the voltage signal is generated by a buffer and a pMOS transistor, therefore the internal power source voltage of the required lowest limit can be supplied in response to the frequency of the clock and a reduction of the voltage and conservation of the electric power of the LSI circuit can be achieved.
摘要翻译：电压控制延迟电路由串联连接的m个门，时钟信号和延迟信号的相位由相位比较器进行比较，输出上升信号或下降信号，积分器产生积分信号，其后的电压信号由缓冲器产生并作为工作电源电压被反馈到压控延迟电路，并且进一步由缓冲器和pMOS晶体管产生跟随电压信号的内部电源电压，因此，可以响应于时钟的频率提供所需最低限制的内部电源电压，并且可以实现电压的降低和LSI电路的电力的保护。

4. 发明授权

US5774007A Clock distributing apparatus having V/I and I/V converters 失效
标题翻译：具有V / I和I / V转换器的时钟分配装置
公开(公告)号：US5774007A
公开(公告)日：1998-06-30
申请号：US730933
申请日：1996-10-16
申请人： Mitsuo Soneda
发明人： Mitsuo Soneda
IPC分类号： G06F1/10 , G11C11/4076 , H01L21/822 , H01L27/04 , H03K5/00 , H03K5/13 , H03L7/18 , H03L7/07
CPC分类号： H03L7/18 , G06F1/10 , H03K5/133
摘要： A clock distributing apparatus which can decrease the clock skew and can prevent the swing of a signal on clock transmission lines and can achieve a low power consumption, a lower noise of a power supply, and a high speed operation, wherein converts clock signals adjusted in phase to the same phase as a reference clock by a PLL circuit to current signals by voltage/current converters and sends the current signals to clock transmission lines and converts the current signals transmitted to the clock transmission lines to voltage signals by current/voltage converters and sends the voltage signals to circuit blocks of an integrated circuit.
摘要翻译：一种时钟分配装置，其可以减小时钟偏移并且可以防止时钟传输线上的信号的摆动，并且可以实现低功耗，较低的电源噪声和高速操作，其中转换时钟信号被调整通过PLL电路与参考时钟相位与电流/电流转换器的电流信号相同，并将电流信号发送到时钟传输线，并将通过电流/电压转换器传输到时钟传输线的电流信号转换为电压信号，将电压信号发送到集成电路的电路块。

5. 发明授权

US4447812A Liquid crystal matrix display device 失效
标题翻译：液晶矩阵显示装置
公开(公告)号：US4447812A
公开(公告)日：1984-05-08
申请号：US384560
申请日：1982-06-03
申请人： Mitsuo Soneda , Takaji Ohtsu
发明人： Mitsuo Soneda , Takaji Ohtsu
IPC分类号： H04N5/66 , G02F1/133 , G09G3/20 , G09G3/36 , H04N3/12 , G09G3/18
CPC分类号： G09G3/3688 , G09G3/3648 , H04N3/127 , G09G2310/0297 , G09G3/2011
摘要： A liquid crystal matrix display device has a plurality of display elements arranged in an X-Y matrix pattern. Vertical transmitting lines are connected to all of the display elements of each column, and horizontal transmitting lines are connected to each of the display elements of each row. Each of the vertical lines is connected through an input switching element to an input circuit to receive a video input signal and a horizontal pulse generator provides sequential pulse signals to control terminals of the input switching elements. In order to improve the resolution without sacrifice of contrast, the vertical transmitting lines are arranged into groups of a predetermined number of such lines, and the input switching elements associated with the lines of each such group have their control electrodes coupled together to a respective output of the horizontal scanning pulse generator. The input circuit includes time-demultiplexing circuitry, for example, formed of sample/hold circuits, to present respective sampled versions of the input signal, staggered with respect to one another, to input electrodes of respective ones of the input switching devices of each of the groups.
摘要翻译：液晶矩阵显示装置具有以X-Y矩阵图案排列的多个显示元件。垂直传输线连接到每列的所有显示元件，并且水平传输线连接到每行的每个显示元件。每个垂直线通过输入开关元件连接到输入电路以接收视频输入信号，并且水平脉冲发生器向输入开关元件的控制端提供顺序脉冲信号。为了在不牺牲对比度的情况下提高分辨率，垂直传输线被布置成预定数量的这样的线的组，并且与每个这样的组的线相关联的输入开关元件的控制电极耦合到相应的输出的水平扫描脉冲发生器。输入电路包括例如由采样/保持电路形成的时分解复用电路，以将相对于彼此交错的输入信号的相应采样版本呈现给每个的各个输入开关装置的输入电极团体。

6. 发明授权

US5856918A Internal power supply circuit 失效
标题翻译：内部电源电路
公开(公告)号：US5856918A
公开(公告)日：1999-01-05
申请号：US743825
申请日：1996-11-05
申请人： Mitsuo Soneda , Akira Li
发明人： Mitsuo Soneda , Akira Li
IPC分类号： H02M3/07 , H02M7/00
CPC分类号： H02M3/07
摘要： An internal power supply circuit, comprising a plurality of charge accumulators, a first power supply terminal, a second power supply terminal, a first switch for connecting the plurality of charge accumulators in parallel to each other in a first state, and a second switch for connecting the plurality of charge accumulators in series with each other in a second state, the charge accumulators connected between the first power supply terminal and the second power supply terminal at either the first state or the second state, and the first state and the second state set repeatedly to raise or lower a voltage between the first power supply terminal and the second power supply terminal.
摘要翻译：一种内部电源电路，包括多个电荷累加器，第一电源端子，第二电源端子，用于在第一状态下彼此并联连接多个电荷累加器的第一开关，以及用于在第二状态下将多个电荷蓄积器彼此串联连接，所述电荷蓄积器在第一状态或第二状态下连接在第一电源端子和第二电源端子之间，而第一状态和第二状态反复设定以提高或降低第一电源端子和第二电源端子之间的电压。

7. 发明授权

US4591916A Solid state image pickup device 失效
标题翻译：固态图像拾取装置
公开(公告)号：US4591916A
公开(公告)日：1986-05-27
申请号：US557180
申请日：1983-11-25
申请人： Mitsuo Soneda , Toshikazu Maekawa , Takaji Ohtsu
发明人： Mitsuo Soneda , Toshikazu Maekawa , Takaji Ohtsu
IPC分类号： H01L27/146 , H01L31/10 , H04N5/335 , H04N5/355 , H04N5/359 , H04N5/369 , H04N5/374 , H04N3/14
CPC分类号： H04N3/1512
摘要： A solid state image pickup device comprises first switching elements (S'.sub.11 to S'.sub.mn) arrayed in horizontal and vertical rows and composed of a plurality of P-channel insulated-gate field-effect transistors, the first switching elements in each vertical row having one terminals connected in common, a photoelectric transducer layer (17) disposed over the horizontal and vertical rows of the first switching elements (S'.sub.11 to S'.sub.mn) and electrically connected to other terminals of the first switching elements (S'.sub.11 to S'.sub.mn), and a plurality of second switching elements (T.sub.1 to T.sub.n) disposed respectively for the vertical rows of the first switching elements (S'.sub.11 to S'.sub.mn) and connected respectively to the one terminals connected in common of the first switching elements in the respective vertical rows, with the arrangement thereof wherein the horizontal rows of the first switching elements (S'.sub.11 to S'.sub.mn) are selectively energizable and the second switching elements (T.sub.1 to T.sub.n) are selectively energizable to deliver signals based on signal charges generated by the photoelectric conversion layer (17) through the first and second switching elements (S'.sub.11 to S'.sub.mn, T.sub.1 to T.sub.n) so as to produce an image pickup signal output.
摘要翻译： PCT No.PCT / JP83 / 00100 Sec。 371日期：1983年11月25日 102（e）1983年11月25日日期PCT提交1983年3月31日PCT公布。出版物WO83 / 03514 日期：1983年10月13日。固态图像拾取装置包括以水平和垂直行排列并由多个P沟道绝缘栅场效应晶体管组成的第一开关元件（S'11至S'mn），每个垂直行中的第一开关元件具有共同连接的一个端子，设置在第一开关元件（S'11至S'mn）的水平和垂直行上并且电连接到第一开关元件的其它端子的光电传感器层（17）第一开关元件（S'11至S'mn）以及分别设置在第一开关元件（S'11至S'mn）的垂直行中的多个第二开关元件（T1至Tn），并分别连接到其各个垂直行中的第一开关元件共同连接的一个端子，其中第一开关元件（S'11至S'mn）的水平行选择性地通电，并且第二开关元件（T1至Tn ）选择性地激励以基于由光电转换层（17）通过第一和第二开关元件（S'11至S'mn，T1至Tn）产生的信号电荷来传送信号，以产生图像拾取信号输出。

8. 发明授权

US4466018A Image pickup apparatus with gain controlled output amplifier 失效
标题翻译：带增益控制输出放大器的摄像装置
公开(公告)号：US4466018A
公开(公告)日：1984-08-14
申请号：US379959
申请日：1982-05-19
申请人： Mitsuo Soneda , Takashi Noguchi , Takaji Ohtsu
发明人： Mitsuo Soneda , Takashi Noguchi , Takaji Ohtsu
IPC分类号： H03G1/00 , H04N5/243 , H04N5/374 , H04N5/378 , H04N5/14
CPC分类号： H03G1/0017 , H03G1/0029 , H04N5/243 , H04N5/335
摘要： Solid-state image pickup apparatus, such as an MOS imager, has a two-dimensional array of picture element units each formed of a photo sensitive element and a gating element. The picture unit elements discharge a signal charge onto vertical and horizontal transmitting lines in response to vertical and horizontal scanning pulses. Then, a resulting signal current is used to develop an output video signal. In order to give the output video signal a good S/N ratio, a gain-controlled current amplifier is employed. In several embodiments, the gain-controlled amplifier includes first through fourth transistors with the base-emitter junctions of the first and second transistors and of the third and fourth transistors connected in series, with a constant current source coupled to the first transistor, controlled current sources connected to the second and third transistors, and a load device coupled to the fourth transistor. In other embodiments, the gain controlled amplifier is formed of first, second, and third current mirror circuits connected in a balanced-current arrangement. Electrically variable resistances, e.g., MOS transistors, are coupled to the output transistors of the first and second current mirror circuits to control the current gain.
摘要翻译：诸如MOS成像器的固态图像拾取装置具有每个由感光元件和选通元件形成的像素单元的二维阵列。图像单元根据垂直和水平扫描脉冲将信号电荷放电到垂直和水平传输线上。然后，使用结果信号电流来产生输出视频信号。为了使输出视频信号具有良好的S / N比，采用增益控制电流放大器。在几个实施例中，增益控制放大器包括第一至第四晶体管，其中第一和第二晶体管的基极 - 发射极结与第三和第四晶体管串联连接，恒定电流源耦合到第一晶体管，受控电流连接到第二和第三晶体管的源极以及耦合到第四晶体管的负载器件。在其他实施例中，增益控制放大器由以平衡电流布置连接的第一，第二和第三电流镜电路形成。电可变电阻例如MOS晶体管耦合到第一和第二电流镜电路的输出晶体管以控制电流增益。

9. 发明授权

US4463383A Image pickup apparatus 失效
标题翻译：摄像设备
公开(公告)号：US4463383A
公开(公告)日：1984-07-31
申请号：US375109
申请日：1982-05-05
申请人： Mitsuo Soneda , Takashi Noguchi , Takaji Ohtsu
发明人： Mitsuo Soneda , Takashi Noguchi , Takaji Ohtsu
IPC分类号： H04N5/14 , H03G1/00 , H04N5/243 , H04N5/335 , H04N5/341 , H04N5/357 , H04N5/372 , H04N5/374 , H04N5/378 , H04N5/197
CPC分类号： H04N5/243 , H03G1/0017 , H03G1/0029 , H04N5/335
摘要： Solid-state image pickup apparatus, such as an MOS imager, has a two-dimensional array of picture element units each formed of a photo sensitive element and a gating element, and scanning circuits for supplying horizontal and vertical scanning pulses. The picture unit elements in turn discharge a signal charge onto vertical and horizontal transmitting lines in response to the vertical and horizontal scanning pulses. Then, a resulting signal current is used to develop an output video signal. In order to provide a strong output video signal with a good S/N ratio, a current mirror circuit, formed of an input transistor and an output transistor with first current-carrying electrodes joined together to a voltage reference point and with control electrodes joined together, amplifies the signal current. A second current-carrying electrode of the input transistor receives a constant current from a current source and also receives the signal current. The output transistor has a second current-carrying electrode connected to an output load. Another current source can be connected to the output transistor so that only AC current will flow to the output load. The output load can be a load capacitor associated with a pre-charging transistor, or can be a serial charge transfer device.
摘要翻译：诸如MOS成像器的固态图像拾取装置具有由光敏元件和选通元件形成的像素单元的二维阵列，以及用于提供水平和垂直扫描脉冲的扫描电路。图像单元元件又响应于垂直和水平扫描脉冲将信号电荷放电到垂直和水平传输线上。然后，使用结果信号电流来产生输出视频信号。为了提供具有良好S / N比的强输出视频信号，由输入晶体管和具有第一载流电极的输出晶体管形成的电流镜电路连接到电压参考点并与控制电极连接在一起，放大信号电流。输入晶体管的第二载流电极从电流源接收恒定电流并且还接收信号电流。输出晶体管具有连接到输出负载的第二载流电极。另一个电流源可以连接到输出晶体管，因此只有交流电流将流向输出负载。输出负载可以是与预充电晶体管相关联的负载电容器，或者可以是串联电荷转移装置。

10. 发明授权

US07355214B2 Field effect transistor and fabrication thereof, semiconductor device and fabrication thereof, logic circuit including the semiconductor device, and semiconductor substrate 有权
标题翻译：场效应晶体管及其制造，半导体器件及其制造，包括半导体器件的逻辑电路和半导体衬底
公开(公告)号：US07355214B2
公开(公告)日：2008-04-08
申请号：US10752705
申请日：2004-01-08
申请人： Takashi Noguchi , Mitsuo Soneda
发明人： Takashi Noguchi , Mitsuo Soneda
IPC分类号： H01L31/0328
CPC分类号： H01L21/823814 , H01L21/823807
摘要： A method for forming a Field Effect Transistor (FET) within a strain effect semiconductor layer is disclosed, whereby the source and drain of the FET are formed only in the strain effect silicon layer. The FET may be formed as a gate electrode of a p-channel type field effect transistor, and a gate electrode of a n-channel type field effect transistor on the silicon layer which has the strain effect through a gate insulating film. The sources and drains of p- and n-type diffusion layers are then formed in the silicon layer having the strain effect, on both sides of the gate electrode.
摘要翻译：公开了一种在应变效应半导体层内形成场效应晶体管（FET）的方法，由此仅在应变效应硅层中形成FET的源极和漏极。 FET可以形成为p沟道型场效应晶体管的栅极电极和在硅层上的n沟道型场效应晶体管的栅极，其通过栅极绝缘膜具有应变效应。然后在具有应变效应的硅层中，在栅电极的两侧形成p型和n型扩散层的源极和漏极。

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