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    • 5. 发明申请
    • TRACK BUFFER IN A PARALLEL DECODER
    • 并行解码器中的缓存器
    • WO2006073732A3
    • 2008-01-24
    • PCT/US2005045544
    • 2005-12-15
    • FREESCALE SEMICONDUCTOR INCWANG BOMACIAS ADRIAN R
    • WANG BOMACIAS ADRIAN R
    • H03M13/03
    • H03M13/6561H03M13/4107
    • A method (700) and apparatus (600) are described for performing 2 exp (M-I) parallel ACS operations to generate 2 exp(M) path metric outputs and buffereing the 2 exp(M) path metric outputs in connection with a track buffer (112) in an Ultrawide Bandwidth (UWB) receiver for decoding a message sequence encoded according to a convolutional code. Contents of the track buffer are updated in accordance with Register Exchange and outputs from the track buffer can further be input to a voting unit (114) where a voting scheme can be applied and a decision rendered as to the originally transmitted message sequence.
    • 描述了一种方法(700)和装置(600),用于执行2个exp(MI)并行ACS操作,以产生2个exp(M)路径度量输出,并且将2个exp(M)路径度量输出结合到一个轨道缓冲器 112)在用于对根据卷积码编码的消息序列进行解码的超宽带(UWB)接收机中。 轨道缓冲器的内容根据寄存器交换进行更新,并且轨道缓冲器的输出可以进一步输入到可以应用投票方案的投票单元(114),并且对最初发送的消息序列做出决定。