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1. 发明专利

AT477631T 未知
公开(公告)号：AT477631T
公开(公告)日：2010-08-15
申请号：AT04815800
申请日：2004-12-28
申请人： MOTOROLA INC
发明人： KHAWAND CHARBEL , TAO JIANPING , VAGLICA JOHN
IPC分类号： H04J3/06 , G06F9/46 , H04L7/00 , H04L23/00
摘要： The invention concerns a method (500) for employing adaptive event codes. The method includes the steps of generating (512) at least one adaptive event code in which the adaptive event code corresponds to a preexisting event code, storing (514) the adaptive event code in at least one table (154, 156), running (516) the table in which the adaptive event codes are at least initially disabled and enabling (522) the adaptive event code in response to a system event in which the preexisting event code that corresponds to the enabled adaptive event code is executed (526). The method can further include the step of ignoring (518) the adaptive event codes during the running step when the adaptive event codes are disabled.

2. 发明专利

AU2002331762A1 Cpu powerdown method and apparatus therefor 未知
公开(公告)号：AU2002331762A1
公开(公告)日：2003-04-01
申请号：AU2002331762
申请日：2002-08-29
申请人： MOTOROLA INC
发明人： VAGLICA JOHN
IPC分类号： G06F1/04 , G06F1/26 , G06F1/32 , G06F15/78
摘要： A CPU has a powerdown mode in which most of the circuitry does not receive power. Power-up, coming out of powerdown, is achieved in response to receiving an exception. Because most of the state information that is present in the CPU is not needed in response to an exception, there is no problem in removing power to most of the CPU during powerdown. The programmer's model register file and a few other circuits in the CPU are maintained in powerdown, but the vast majority of the circuits that make up the CPU: the execution unit, the instruction decode and control logic, instruction pipeline and bus interface, do not need to receive power. Removing power from these non-critical circuits results in significant power savings during powerdown. The powered circuits are provided with a reduced power supply voltage to provide additional power savings.

3. 发明申请

WO03025728A2 CPU POWERDOWN METHOD AND APPARATUS THEREFOR 审中-公开
标题翻译： CPU POWERDOWN方法及其设备
公开(公告)号：WO03025728A2
公开(公告)日：2003-03-27
申请号：PCT/US0227589
申请日：2002-08-29
申请人： MOTOROLA INC
发明人： VAGLICA JOHN
IPC分类号： G06F1/04 , G06F1/26 , G06F1/32 , G06F15/78
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F1/3296 , G06F9/3867 , G06F9/3869 , Y02D10/128 , Y02D10/152 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： A CPU (10) has a powerdown mode in which most of the circuitry does not receive power. Power-up (64), coming out of powerdown (58), is achieved in response to receiving an exception (60). Because most of the state information that is present in the CPU (10) is not needed in response to an exception (60), there is no problem in removing power to most of the CPU (10) during powerdown (58). The programmer s model register file (16) and a few other circuits in the CPU (10) are maintained in powerdown (58), but the vast majority of the circuits that make up the CPU (10): the execution unit (20), the instruction decode and control logic (18), instruction pipeline (26) and bus interface (32), do not need to receive power. Removing power from these non-critical circuits results in significant power savings during powerdown. The powered circuits are provided with a reduced power supply voltage to provide additional power savings.
摘要翻译： CPU（10）具有掉电模式，其中大多数电路不接收电力。响应于接收到异常（60），实现了启动（64），断电（58）。由于响应于异常（60）而不需要存在于CPU（10）中的大部分状态信息，所以在关机（58）期间，在大部分CPU（10）中去除电源没有问题。程序员的型号寄存器文件（16）和CPU（10）中的其他电路被维持在掉电状态（58），但构成CPU（10）的绝大多数电路：执行单元（20）指令解码和控制逻辑（18），指令流水线（26）和总线接口（32）不需要接收功率。从这些非关键电路移除电源可在断电期间节省大量功耗。供电电路具有降低的电源电压以提供额外的功率节省。

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