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1. 发明专利

JP2012069567A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012069567A
公开(公告)日：2012-04-05
申请号：JP2010210846
申请日：2010-09-21
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： YUYA NAOKI
IPC分类号： H01L27/04 , H01L21/66 , H01L21/822 , H01L29/06 , H01L29/47 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method therefor, having TEG usable for a semiconductor element formed of a semiconductor other than of silicon.SOLUTION: A semiconductor device 1a includes an SBD portion 2a and a TEG portion 3a for measuring the electric characteristics of the SBD portion 2a. The SBD portion 2a includes: an n-type SiC drift layer 8; and a first Schottky electrode 13 formed on the SiC drift layer 8 with contact to the surface 9 of the SiC drift layer 8. The TEG portion 3a includes: a p-type ion implantation layer 18a formed on a point including the surface 9 of the SiC drift layer 8; a second Schottky electrode 21a formed on the SiC drift layer 8 with contact to the surface 9 of the SiC drift layer 8; and an electrode pad 22 formed on the ion implantation layer 18a with electric connection to the second Schottky electrode 21a, in a manner not to contact to the SiC drift layer 8.
摘要翻译：要解决的问题：为了提供一种可用于由硅以外的半导体形成的半导体元件的TEG的半导体器件及其制造方法。解决方案：半导体器件1a包括用于测量SBD部分2a的电特性的SBD部分2a和TEG部分3a。 SBD部分2a包括：n型SiC漂移层8; 以及形成在与SiC漂移层8的表面9接触的SiC漂移层8上的第一肖特基电极13.TEG部分3a包括：p型离子注入层18a，形成在包括所述SiC漂移层8的表面9的点上 SiC漂移层8; 形成在与SiC漂移层8的表面9接触的SiC漂移层8上的第二肖特基电极21a; 以及以不与SiC漂移层8接触的方式形成在与第二肖特基电极21a电连接的离子注入层18a上的电极焊盘22.版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2010062402A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010062402A
公开(公告)日：2010-03-18
申请号：JP2008227773
申请日：2008-09-05
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： YUYA NAOKI
IPC分类号： H01L29/12 , H01L21/28 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, improved in mass productivity, yield, and reliability.
SOLUTION: The method for manufacturing a nitride semiconductor device includes a step in which a first contact hole 12 which partially exposes a source region 3 surface and a p+ contact region 5 surface is formed by etching a gate oxide film 6 and an interlayer oxide film 9, and at the same time, a second contact hole 13 which partially exposes a gate electrode 7 surface on the upper side of a drift region 2 is formed by etching the interlayer oxide film 9. It also includes a step in which a first oxide film is formed by thermally oxidizing the exposed upper part of a source region 3 and the upper part of p+ contact region 5, and at the same time, an oxide film 16 which is thicker than the first oxide film is formed by thermally oxidizing the exposed upper part of gate electrode 7. It further includes steps of: totally removing the first oxide film while leaving the oxide film 16 alone; forming an Ni film 17; and forming an NiSi film 18 by the first annealing.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，提高了批量生产率，产量和可靠性。解决方案：用于制造氮化物半导体器件的方法包括以下步骤：通过蚀刻栅极氧化膜6和中间层形成部分地暴露源极区3表面和p +接触区5表面的第一接触孔12 氧化膜9，并且同时，通过蚀刻层间氧化膜9形成部分地暴露漂移区2的上侧的栅电极7表面的第二接触孔13.其还包括以下步骤：通过热源氧化源极区3的上部和p +接触区5的上部来形成第一氧化膜，同时通过热氧化形成比第一氧化物膜厚的氧化膜16 露出的栅极电极7的上部。还包括以下步骤：在仅留下氧化膜16的同时完全除去第一氧化物膜; 形成Ni膜17; 并通过第一退火形成NiSi膜18。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2009130244A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009130244A
公开(公告)日：2009-06-11
申请号：JP2007305586
申请日：2007-11-27
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： WATANABE HIROSHI , YUYA NAOKI , OTSUKA KENICHI , MIURA NARIHISA , TARUI YOICHIRO
IPC分类号： H01L29/78 , H01L21/28 , H01L29/12 , H01L29/41 , H01L29/417 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To reduce channel resistance in a vertical semiconductor device wherein a p-type source contact part is disposed in a p-type semiconductor region of a cell corner part.
SOLUTION: The semiconductor device has: a p-type bridge layer 12 which is disposed in a surface layer part of an n
- type drift layer 2 and connects a p-type base layer 3; an n
+ type conductive layer 14 which is formed apart from a p-type source layer 4 by a second distance in a marginal part of the p-type bridge layer 12; and a p
+ type contact layer 13 enclosed with the n
+ type conductive layer 14. It also has: a channel region between the n
+ type source layer 4 and the n
- type drift layer 2; and a gate electrode 6 formed in a channel region between the n
+ type source layer 4 and the n
+ type conductive layer 14 via a gate insulating film 5. The p
+ type contact layer 13 is formed deeper than the n
+ type conductive layer 14 and shallower than the p-type bridge layer 12. The n
+ type conductive layer 14 is constituted in continuity with the n
- type drift layer 2.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了降低其中p型源极接触部分设置在电池角部分的p型半导体区域中的垂直半导体器件中的沟道电阻。解决方案：半导体器件具有：p型桥接层12，其设置在n型SP型漂移层2的表层部分中，并连接p型基极层3; 在p型桥接层12的边缘部分中与p型源极层4隔开第二距离形成的n + 型导电层14; 以及由n + 型导电层14包围的ap + 型接触层13.它还具有：n + 型之间的沟道区源层4和n - / SP>型漂移层2; 以及通过栅极绝缘膜5形成在n + SP型源极层4和n + / SP>型导电层14之间的沟道区域中的栅电极6。 SP> + 型接触层13形成得比n型SP + + / SP型导电层14深，并且比p型桥接层12浅。型导电层14与n - SP型漂移层2连续地构成。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2007280978A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2007280978A
公开(公告)日：2007-10-25
申请号：JP2006101386
申请日：2006-04-03
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TARUI YOICHIRO , YUYA NAOKI , WATANABE HIROSHI
IPC分类号： H01L21/027
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of preventing an alignment mark used for overlapping in a manufacturing process from being deformed asymmetrically in a heat-treatment process, such as activation annealing treatment and epitaxial growth in a manufacturing process in the semiconductor device using SiC for a substrate.
SOLUTION: The method for manufacturing the semiconductor device using SiC for the substrate comprises: a process for forming an alignment mark 2 on a {0001} plane in the SiC substrate 1; and a process for forming a prescribed pattern on the SiC substrate 1 by aligning a transfer mask and the SiC substrate 1, based on the alignment mark 2.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种制造半导体器件的方法，该半导体器件能够防止在制造工艺中用于重叠的对准标记在热处理工艺中不对称地变形，例如激活退火处理和外延生长在使用SiC用于衬底的半导体器件中的制造工艺。解决方案：用于制造使用SiC的半导体器件用于衬底的方法包括：在SiC衬底1中的ä0001}面上形成对准标记2的工艺; 以及通过基于对准标记2对转印掩模和SiC基板1在SiC基板1上形成规定图案的工序。（C）2008，JPO＆INPIT

5. 发明专利

JP2007273727A Alignment mark, and forming method therefor, and semiconductor device and manufacturing method therefor 有权
标题翻译：对准标记及其形成方法及其半导体器件及其制造方法
公开(公告)号：JP2007273727A
公开(公告)日：2007-10-18
申请号：JP2006097553
申请日：2006-03-31
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： WATANABE HIROSHI , YUYA NAOKI , TARUI YOICHIRO
IPC分类号： H01L21/027
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an alignment mark that is restrained in deterioration of positioning accuracy, even after passage of an epitaxial film deposition process and high-temperature annealing process.
SOLUTION: The alignment mark 14 is formed by a stepwise step difference pattern in a cross-sectional shape. The step difference pattern includes a first step difference pattern 11, formed by digging down a principal surface of a substrate 2; and a second step difference pattern 13, formed by further digging down the principal surface of the substrate 2, in continuation with the first step difference pattern 11 below the first step difference pattern 11 formed by digging down the principal surface of the substrate 2. A sidewall part 17 of the first step difference pattern 11 and a sidewall part 18 of the second step difference pattern 13 are formed at the same angle and is formed so as to have the same crystal orientation.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：即使在通过外延膜沉积工艺和高温退火工艺之后，也提供限定在定位精度降低的对准标记。解决方案：对准标记14由横截面形状的逐步阶差分图形形成。台阶差分图案包括通过挖掘基板2的主表面而形成的第一阶差分图案11; 以及通过进一步向下挖掘基板2的主表面而形成的第二阶梯差异图案13，其与通过挖掘基板2的主表面而形成的第一阶梯差异图案11之下的第一阶梯差异图案11连续。第一台阶差异图案11的侧壁部17和第二台阶差异图案13的侧壁部18以相同的角度形成，并且形成为具有相同的晶体取向。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2002365154A PRESSURE DETECTOR 失效
公开(公告)号：JP2002365154A
公开(公告)日：2002-12-18
申请号：JP2001173984
申请日：2001-06-08
申请人： MITSUBISHI ELECTRIC CORP
发明人： FUJINO CHIYO , HAMADA SHINGO , KOTO SATORU , OJI HIROSHI , YUYA NAOKI
IPC分类号： G01L11/00
摘要： PROBLEM TO BE SOLVED: To allow accurate measurement for fluid pressure. SOLUTION: A pressure measuring instrument 10 has a pressure receiving sheet (diaphragm) 16 defined between the first face included in a reference face 28, and the second face contacting with a fluid, and deformed in response to the pressure of the fluid, a substrate 40 arranged to be opposed to the reference face, two thermosensitive resistors 48, 50 held opposedly to the reference face by the substrate, and at least two spacers 62 arranged between the reference face and the substrate to hold a space between the reference face and the substrate at constant spacing. The thermosensitive resistors and the spacers are arranged to make two thermosensitive resistors positioned on the same contour on a displacement distribution diagram along the direction vertical to the reference face drawn as to the substrate when the substrate is deformed to the direction opposed to the pressure receiving sheet.

7. 发明专利

JPH06153078A SOLID-STATE IMAGE PICKUP DEVICE 失效
公开(公告)号：JPH06153078A
公开(公告)日：1994-05-31
申请号：JP29132792
申请日：1992-10-29
申请人： MITSUBISHI ELECTRIC CORP
发明人： YUYA NAOKI
IPC分类号： H01L29/762 , H01L21/339 , H04N5/335 , H04N5/341 , H04N5/355 , H04N5/361 , H04N5/369 , H04N5/3728 , H04N5/378 , H01L29/796
摘要： PURPOSE:To enlarge a numerical aperture by improving a charge transfer ability without increasing power consumption. CONSTITUTION:A photodetector 1 stores a signal charge generated by photoelectric conversion. When a fetching pulse signal is impressede to an electrode 3 arranged on a CSD channel 2 from an interlace circuit 6, the signal charge is fetched from the photodetector 1 to the CSD channel 2 under the electrode 3 by way of a transfer gate 30. Then, when a vertical transfer pulse is impressed from a CDS scanner circuit 7 to respective electrodes 3, 3,..., the signal charge is transferred toward a storage gate 8 by plural charge bucket formed within the CSD channel 2. The storage gate 8 receives and stores the transferred signal charge. The amplitude of a vertical transfer pulse signal impressed from the CSD scanner circuit 7 to the electrodes 3, 3,... is reduced along with time.

8. 发明专利

JPH04186673A SOLID-STATE INFRARED IMAGE SENSOR 失效
公开(公告)号：JPH04186673A
公开(公告)日：1992-07-03
申请号：JP31254590
申请日：1990-11-16
申请人： MITSUBISHI ELECTRIC CORP
发明人： YUYA NAOKI
IPC分类号： H01L27/146 , H01L27/14 , H01L31/108
摘要： PURPOSE:To facilitate the sensitivity control of an image sensor by providing slits in a metal electrode forming the Schottky junction of a photodetector so that the insensitive area around the individual slits may vary depending on the voltage applied to a reflecting film of aluminum. CONSTITUTION:A schottky diode has a metal electrode 2 as a photoelectric layer with slits 31. The metal electrode is insensitive to light at the slits where inversion to n-type occurs by application of a voltage to a reflective aluminum layer 11. The inversion area spreads as the applied voltage increases; that is, the insensitive area increases. Since the insensitive area varies with the applied voltage, sensitivity can be easily controlled according to the amount of light incident to the device.

9. 发明专利

JPH04111467A INFRARED SOLID STATE IMAGE PICKUP DEVICE 失效
公开(公告)号：JPH04111467A
公开(公告)日：1992-04-13
申请号：JP23140490
申请日：1990-08-31
申请人： MITSUBISHI ELECTRIC CORP
发明人： YUYA NAOKI
IPC分类号： H01L27/148 , H01L27/14
摘要： PURPOSE:To increase the reset voltage dependence of optical sensitivity in an infrared detector and facilitate the change of the optical sensibility by said reset voltage by forming an impurity intake passage which introduces a specified amount of impurities into a Schottky barrier diode interface on a semiconductor side. CONSTITUTION:An infrared light which enters from the rear side of a p type silicon semiconductor substrate 1 reaches an optical conversion layer 2 of a Schottky junction for photoelectric conversion where generated optical signal load is once stored by the Schottky junction and then it is transferred to an n type buried channel 5 by applying a read out pulse to a gate electrode 6 from a TG scanner 25. When a region 12 in which a specified amount of n type impurities are introduced, is formed on the interface of a p type substrate side 1 of the Schottky junction, the relation between reset voltage and the amount of output signal is turned in linear mode. If an attempt is made to set the voltage VTG of 'H' level of a read out pulse of a TG scanner 25 under this condition, the reset voltage will depend on the voltage VTG of the 'H' level, which makes it possible to control optical sensitivity by means of luminous energy which enters.

10. 发明专利

JPH02208969A SOLID-STATE IMAGE SENSING DEVICE 失效
公开(公告)号：JPH02208969A
公开(公告)日：1990-08-20
申请号：JP2889389
申请日：1989-02-08
申请人： MITSUBISHI ELECTRIC CORP
发明人： YUYA NAOKI
IPC分类号： H01L27/14 , H04N5/335 , H04N5/369
摘要： PURPOSE:To improve a solid-state image sensing device of this design in cooling efficiency by a method wherein the I/O pad of an image sensing element is exposed outside of a support, and a heat transfer path which connects a cooling head with the image sensing element is formed of the support and two adhesive layers. CONSTITUTION:In an image sensing device A, infrared rays X introduced from an optical system to a case 1 is focused on a photoelectric conversion section 32, which optical signal is taken outside through a wire 30, a wire connection pad 24, a inner wiring 25, an external connection lead 26, and an output pin via an I/O pad 31. In this case, a heat transfer path which connects a cooling head 4 with a chip 27 can be formed of a support 21 and adhesive layers 23 and 28, so that it can be made small in heat resistance and heat capacity. By this setup, an image sensing device of this design can be cooled down to a temperature that it can be operable soon after a cooling head starts to operate and surely improved in cooling efficiency.

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