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1. 发明专利

JP2001258139A ANCHOR MECHANISM OF ELECTRIC PLACE 失效
公开(公告)号：JP2001258139A
公开(公告)日：2001-09-21
申请号：JP2000064429
申请日：2000-03-09
申请人： MITSUBISHI ELECTRIC CORP , CHUBU ELECTRIC POWER
发明人： OGURA SHINZO , TSUCHIE AKIRA , TAKAHASHI KAZUYOSHI , MAKINO HIROYUKI , FUKUI KATSUYUKI
IPC分类号： H02G1/02 , H02G7/00
摘要： PROBLEM TO BE SOLVED: To reduce a temperature rise of an iron steel material constituting ground lines and an anchor mechanism by decreasing an induced current flowing to the ground lines for grounding the anchor mechanism. SOLUTION: In the anchor mechanism for anchoring bus bars 1a to 4a from a transmission line and drawing the bars 1a to 4a to a transforming equipment side, respective one legs of the anchor mechanisms 7a to 7e are connected to an underground ground mesh 10 via rising ground lines 9a to 9e. In this case, leading shunt lines 11a to 11e for distributing the induced currents flowing to the lines 9a to 9e are connected to the legs different from the legs of the mechanism.

2. 发明专利

JPH10257671A ELECTRONIC CIRCUIT DEVICE 失效
公开(公告)号：JPH10257671A
公开(公告)日：1998-09-25
申请号：JP6152497
申请日：1997-03-14
申请人： MITSUBISHI ELECTRIC CORP
发明人： MAKINO HIROYUKI
IPC分类号： H01L27/04 , G05F3/20 , H01L21/822 , H02J1/00 , H02M9/04 , H03F1/00 , H03K19/00
摘要： PROBLEM TO BE SOLVED: To reduce power consumption, while maintaining a device to be compact and inexpensive by electrically connecting at least one of a plurality of semiconductor elements in parallel with each of a plurality of electronic circuits for each connection point of a plurality of electronic circuits. SOLUTION: Electronic circuit blocks 13 and 14 are connected in series between a power supply terminal 11 and a ground terminal 12. Further, semiconductor elements 15-18 are connected in series in the forward direction between the power supply terminal 11 and the ground terminal 12. A connection point 19 between the electronic circuit blocks 13 and 14 and a connection point 20 between semiconductor elements 16 and 17 are short-circuited electrically. Thus the current flowing from power supply terminal 11 to the ground terminal 12 becomes the smaller of i1 and i2 at all times, regardless of the relationship in size of the current i1 which flows through the electronic circuit block 13 and the current i2 which flows through the electronic circuit block 14, thereby reducing power consumption.

3. 发明专利

JPH03241590A GALLIUM ARSENIDE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH03241590A
公开(公告)日：1991-10-28
申请号：JP3710390
申请日：1990-02-16
申请人： MITSUBISHI ELECTRIC CORP
发明人： MATSUE SHUICHI , MAKINO HIROYUKI
IPC分类号： G11C11/41 , G11C11/401
摘要： PURPOSE:To reduce a Y-decoder part by providing a column selection line which crosses across plural memory cell arrays and extends in a prescribed direction as against the Y-decoder part and transmitting a decoder output to bit lines. CONSTITUTION:The column selection line 5 which crosses across the memory cell arrays 1a-1d and extends in the prescribed direction from the Y-decoder 4 is provided. Then, the bit lines 2a-2d of respective arrays 1a-1d are respective ly connected with the selection line 5 and the Y-decoder output is transmitted to respective bit lines 2a-2d. Consequently, the Y-decoder part can be reduced without the need of provided the Y-decoders for two pairs of memory cell arrays and the drawing distance of a wiring group connected to the Y-decoder part becomes short, whereby the increase of a chip area can be prevented.

4. 发明专利

JPH03228291A GAAS SEMICONDUCTOR STORAGE 失效
公开(公告)号：JPH03228291A
公开(公告)日：1991-10-09
申请号：JP2390390
申请日：1990-02-01
申请人： MITSUBISHI ELECTRIC CORP
发明人： MAKINO HIROYUKI , MATSUE SHUICHI
IPC分类号： G11C11/412 , H01L27/095 , H01L27/10
摘要： PURPOSE:To improve the resistance to a soft error by providing a means which connects the anode of a Schottky diode to each storage node of a memory cell with the cathode potential set usually at the value slightly higher than a GND level and heightens the potential in a data writing period. CONSTITUTION:Each memory cell contains a 1st Schottky diode 13 which uses a 1st output node 8 and a medium node 15 as an anode and a cathode respectively, a second Schottky diode 14 which uses a 2nd output node 9 and the intermediate node 15 as an anode and a cathode respectively, and a means 21 which heighten the potential of the node 15 of a memory cell of a row or a column to be selected with the potential of the node 15 of a memory cell of a non- selection row or a non-selection column in a data writing period. In such a constitution, the cathode potential is usually set at the value slightly higher than a GND level and then heightened more in a data writing period. Thus the capacity can be added without reducing the voltage amplitudes of storage nodes 8 and 9 nor delaying the writing time. Then the resistance is improved to a soft error.

5. 发明专利

JPH01134800A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH01134800A
公开(公告)日：1989-05-26
申请号：JP29351787
申请日：1987-11-19
申请人： MITSUBISHI ELECTRIC CORP
发明人： MATSUE SHUICHI , TAKANO SATOSHI , MAKINO HIROYUKI
IPC分类号： G11C29/00 , G11C11/34 , G11C11/413 , G11C29/04
摘要： PURPOSE:To easily recognize an error generation in a memory cell from an external part by, when a soft error is generated in the memory cell, detecting it by means of an error detecting circuit and outputting a signal. CONSTITUTION:When the information of equal bit lines BL and the inverse of BL is stored in two storage circuits 2a and 2b of a memory cell 1 by receiving the signal from an equal word line WL, storage nodes N1 and N3 are held at an equal level, and storage nodes N2 and N4 are held at the equal level opposite to that of the storage nodes N1 and N3. A difference between the storage nodes N1, N3 and N2, N4 of a circuit made into the equal level at an ordinary time is generated, an error detecting circuit 3 detects the difference, and the signal is outputted. Thus, that the error is generated in the memory cell 1 can be recognized from the external part.

6. 发明专利

JPS63160382A MANUFACTURE OF MESFET 失效
公开(公告)号：JPS63160382A
公开(公告)日：1988-07-04
申请号：JP30981386
申请日：1986-12-24
申请人： MITSUBISHI ELECTRIC CORP
发明人： MATSUE SHUICHI , TAKANO SATOSHI , MAKINO HIROYUKI
IPC分类号： H01L29/812 , H01L21/28 , H01L21/338 , H01L29/80
摘要： PURPOSE:To contrive high speed operations and high integration by forming a metal film on an N-type impurity layer of the gallium arsenic substrate surface and then by etching a resist film after forming it on the surface of the metal film, thereby forming a gate electrode on sidewalls below the resist film and also by forming source and drain electrode on both sides of the electrode with the vaporization to the surface of the N-type impurity layer. CONSTITUTION:An N-type impurity layer 2 is formed on the substrate surface 1 by ion- implanting silicon atoms into a gallium arsenic substrate 1. And a metal film having a high melting point is formed by spattering metals having a high melting point such as Ti/W over the N-type impurity layer surface 2 after annealing its N-type impurity layer 2. After that, a resist film 3 is formed at the prescribed part of its metal film surface having the high melting point. And then, a gate electrode 10 is formed by performing isotropic etching treatment of the metal film having the high melting point by using the resist film 3 as a mask. The lateral etching amount of the gate electrode 10 is adjusted by the intensity of etching. The utilization of resist film 3 as the mask allows AuGe/Ni/Au to be attached to the N-type impurity layer surface 2 by vaporization and the gate electrode to self-consistently form source and drain electrodes 7 and 8. Further, an AuGe/Ni/Au film 11 is formed even on the resist film surface 3. After that, the unnecessary film 11 and resist film 3 are removed and a sinter process is carried out for the gate electrode 10 as well as the source and drain electrodes 7 and 8.

7. 发明专利

JPS6236918A GALLIUM ARSENIDE SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6236918A
公开(公告)日：1987-02-17
申请号：JP17633485
申请日：1985-08-09
申请人： MITSUBISHI ELECTRIC CORP
发明人： MAKINO HIROYUKI , TAKANO SATOSHI
IPC分类号： H01L21/8222 , H01L27/082 , H03K19/0952
摘要： PURPOSE:To inserr a lvel conversion circuit between 2-stage of series connection E/D inverter circuits so as to descend the low level into a negative potential. CONSTITUTION:A logic signal from a node 10 is inverted by an inverter and its level is subjected to level conversion by a level conversion circuit comprising a normally-off metal-semiconductor FET (MESFET) 5, a Schottky diode 7 and a normally-on MESFET 2. The high level to a level of a node 11 is selected equal to the high level of the internal logic amplitude of an E/D direct coupled FET logic circuit and the low level is brought into a common potential by selecting properly the circuit constant of the conversion circuit and the negative power supply of a node 13. In this case, the normally-off MESFET 6 is turned off completely to a low level of the node 13 regardless of the variation in the thereshold voltage and the inverter comprising the normally-on MESFET 3 and the normally-off MESFET 6 gives always normal inverting operation.

8. 发明专利

JPH113157A BUS DRIVER CIRCUIT 失效
公开(公告)号：JPH113157A
公开(公告)日：1999-01-06
申请号：JP15410197
申请日：1997-06-11
申请人： MITSUBISHI ELECTRIC CORP
发明人： SUZUKI HIROAKI , MAKINO HIROYUKI
IPC分类号： G06F3/00 , G11C11/407 , H03K19/0175
摘要： PROBLEM TO BE SOLVED: To reduce power consumption by suppressing leakage current of a driver transistor without connecting leakage cut switches in series at a power supply side and an installation side with the driver transistor by constituting a bus driver circuit to omit a sleeve signal by matching the sleeve signal and an enable signal. SOLUTION: Each of the sleeve signals SL and SL is supplied to the bus driver circuit 21. Voltage VPP which is higher than power supply voltage VDD is generated by a high voltage generation circuit 13 and voltage VBB which is lower than ground voltage GND is generated by a low voltage generation circuit 14. Control signals S1, S2 are generated by a state control circuit 12 and the voltage VPP which is higher than the VDD as the sleeve signal SL and the voltage GND are selectively outputted according to the control signal S1 by a selection circuit 15. Or the voltage VDD as the sleeve signal SL and the voltage VBB which is lower than the GND are selectively outputted according to the control signal S2 by a selection circuit 16.

9. 发明专利

JPH09305374A SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS POWER CONSUMPTION REDUCING METHOD 失效
公开(公告)号：JPH09305374A
公开(公告)日：1997-11-28
申请号：JP11753696
申请日：1996-05-13
申请人： MITSUBISHI ELECTRIC CORP
发明人： MORINAKA HIROYUKI , MAKINO HIROYUKI , UEDA KIMIHIRO , MASUKO KOICHIRO
IPC分类号： G06F13/38 , G06F1/32 , G06F5/00 , H03K19/00 , H04L25/02
摘要： PROBLEM TO BE SOLVED: To reduce the power consumption. SOLUTION: A comparator 22 outputs bit of the same level among mutually corresponding bits of a last input stored in a register 21 and a current input as an input signal 1. A zero counter 23 counts the bits of the same level outputted by the comparator 22. When the count value is less than a predetermined number, the current input is not similar to the last input, so the inversion of the current input is indicated to a flip-flop 11. The current input is inverted and then the current input becomes similar to the last input, so the power consumption of logic 12 is reducible.

10. 发明专利

JPH05136350A LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH05136350A
公开(公告)日：1993-06-01
申请号：JP29473991
申请日：1991-11-12
申请人： MITSUBISHI ELECTRIC CORP
发明人： MAKINO HIROYUKI , NAKASE YASUNOBU , UEDA KIMIHIRO
IPC分类号： H01L21/8249 , H01L27/06 , H03K19/013 , H03K19/0944
摘要： PURPOSE:To achieve the high-speed operation of the title device by a method wherein a first resistance means and a second resistance means are connected across respective control electrodes for two bipolar transistors which are operated complementarily and the means control the charging speed and the discharging speed of parasitic capacity on the control electrodes of the respective bipolar transistors. CONSTITUTION:When an input logic is changed from a high level to a low level, a P-channel MOSPET 1 is first set to an ON state and an N-channel MOSFET 2 is then set to an OFF state. Consequently, an electric current flows from a high-potential point 8 to a node 7 via the P-channel MOSFET 1 and a resistance 12, and the potential of the node 7 is raised. At this time, the base capacity of an NPN transistor 3 is charged, and also the base capacity of a PNP transistor 4 is charged via resistances 12, 13. When the potential of the node 7 is raised, the base capacity of the NPN transistor 3 is charged at a speed which is slower than that of the base capacity of the PNP transistor 4. As a result, a base potential is raised quickly.

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