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1. 发明专利

FR2617969A1 APPAREIL D'EVALUATION DE CONTRAINTES 未知
公开(公告)号：FR2617969A1
公开(公告)日：1989-01-13
申请号：FR8809166
申请日：1988-07-06
申请人： MITSUBISHI ELECTRIC CORP , MITSUBISHI ELECTRIC CORP
发明人： INOUE YASUO , YASUO INOUE
IPC分类号： G01L1/24 , G01L1/00 , G01N21/65
摘要： Un appareil d'évaluation de la contrainte interne existant dans un matériau, par différence entre des nombres d'onde de pic de spectres Raman de lumière diffusée, comprend notamment des moyens de changement de température 8 destinés à changer la température de points de mesure; des moyens de traitement statistique 6 qui traitent statistiquement, pour chaque point de mesure, un ensemble de valeurs mesurées d'un nombre d'onde de pic variant en fonction du changement de température; et des moyens arithmétiques 7 qui déterminent la relation entre le changement de température des points de mesure et la variation du nombre d'onde, sur la base des valeurs statistiques calculées, permettant ainsi d'obtenir un nombre d'onde de pic à une température de référence déterminée.

2. 发明专利

DE69215429D1 未知
公开(公告)号：DE69215429D1
公开(公告)日：1997-01-09
申请号：DE69215429
申请日：1992-05-06
申请人： MITSUBISHI ELECTRIC CORP
发明人： TSUTSUMI KAZUHITO , ASHIDA MOTOI , INOUE YASUO
IPC分类号： H01L21/336 , H01L21/8244 , H01L21/8247 , H01L27/11 , H01L29/78 , H01L29/786 , H01L29/788 , H01L29/792 , H01L29/772 , H01L21/82
摘要： A structure of a thin film transistor capable of reducing the power consumption in the waiting state and stabilizing the data holding characteristic in application of the thin film transistor as a load transistor in a memory cell in a CMOS-type SRAM is provided. A gate electrode (1) is formed of a polycrystalline silicon film on a substrate (1000) having an insulating property. A gate insulating film (2) is formed on the gate electrode (1). A polycrystalline silicon film (3) is formed on the gate electrode (1) with the gate insulating film (2) interposed therebetween. Source/drain regions including a region (6) of low concentration and a region (8) of high concentration are formed in one and another regions of the polycrystalline silicon film (3) separated by the gate electrode (1). Thus, the thin film transistor is formed. The thin film transistor is applied to p-channel MOS transistors (35, 36) serving as load transistors in a memory cell of a CMOS-type SRAM. P-channel MOS transistors (35, 36) are connected to n-channel MOS transistors (33, 34) serving as driver transistors in the memory cell. The n-channel MOS transistors (33, 34) are formed in a p-type well region (500), and the p-channel MOS transistors (35, 36) are formed on an interlayer insulating film (111) on the n-channel MOS transistors (33, 34).

3. 发明专利

GB2186363B APPARATUS AND METHOD FOR DETERMINING CRYSTAL ORIENTATION 未知
公开(公告)号：GB2186363B
公开(公告)日：1989-11-22
申请号：GB8702091
申请日：1987-01-30
申请人： MITSUBISHI ELECTRIC CORP
发明人： INOUE YASUO , NISHIMURA TADASHI , SUGAHARA KAZUYUKI , KUSUNOKI SHIGERU
IPC分类号： H01L21/66 , G01N21/00 , G01N21/21 , G01N21/65 , G01N21/84

4. 发明专利

FR2594227A1 未知
公开(公告)号：FR2594227A1
公开(公告)日：1987-08-14
申请号：FR8701460
申请日：1987-02-06
申请人： MITSUBISHI ELECTRIC CORP
发明人： INOUE YASUO , NISHIMURA TADASHI , SUGAHARA KAZUYUKI , KUSUNOKI SHIGERU
IPC分类号： G01N21/21 , G01N21/65 , G01N21/84
摘要： In a method for determining orientation of a crystal with polarization selective Raman microprobe spectroscopy, polarization angles of both light incident on the crystal and Raman scattered light emitted from the crystal are varied coincidently in ordinary circumstances and only either one of the polarization angles is varied in only case that intensity of the scattered beam does not change substantially in spite of the coincident variation of both the polarization angles.

5. 发明专利

DE4443968B4 未知
公开(公告)号：DE4443968B4
公开(公告)日：2004-07-15
申请号：DE4443968
申请日：1994-12-09
申请人： MITSUBISHI ELECTRIC CORP
发明人： MAEDA SHIGENOBU , INOUE YASUO , KURIYAMA HIROTADA , MAEGAWA SHIGETO , KANAMOTO KYOZO , IWAMATSU TOSHIAKI
IPC分类号： H01L27/10 , H01L21/77 , H01L21/8242 , H01L21/84 , H01L27/06 , H01L27/108 , H01L27/12 , H01L29/78 , H01L29/786
摘要： A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a storage node, are disposed on the first impurity diffusion layer. A capacitor insulating film is disposed on a second conductive layer. A cell plate is disposed on a storage node with the capacitor insulating film therebetween. A capacitance of the bit line is reduced, and a dynamic random access memory thus constructed performs a high-speed operation.

6. 发明专利

DE10135557A1 Semiconductive device used in complementary metal oxide semiconductor transistor, sequentially comprises substrate, conductive silicon film, silicide film, barrier film, and metal film 未知
公开(公告)号：DE10135557A1
公开(公告)日：2002-02-07
申请号：DE10135557
申请日：2001-07-20
申请人： MITSUBISHI ELECTRIC CORP
发明人： HAYASHI KIYOSHI , INOUE YASUO
IPC分类号： H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/78 , H01L21/336 , H01L21/3205
摘要： A semiconductive device comprises a substrate, a conductive silicon film overlying the substrate, a silicide film overlying the conductive silicon film, a barrier film overlying the silicide film, and a metal film overlying the barrier film. The silicide film contains metal and silicon. A semiconductive device comprises a substrate (1), a conductive silicon film (3) overlying the substrate, a silicide film (4) overlying the conductive silicon film, a barrier film (5) overlying the silicide film, and a metal film (6) overlying the barrier film. The silicide film contains metal and silicon. The barrier film contains metal, nitrogen and silicon; silicon, and oxygen and/or nitrogen; and/or metal and nitrogen. Independent claims are also included for (A) a method of manufacturing the semiconductor device, and (B) a complementary metal oxide semiconductor (CMOS) transistor comprising at least two semiconductor devices. The method comprises patterning the conductive silicon film, the silicide film, the barrier film and the metal film by photolithography and etching. The conductive silicon film, the silicide film, the barrier film and the metal film are used as gate electrodes for the CMOS transistor. A gate insulating film (2) is disposed between the substrate and the conductive silicon film of the respective semiconductor devices. Well and source/drain regions are disposed in the substrate. The conductive silicon films of the two semiconductor devices are electrically connected.

7. 发明专利

DE19750378A1 Semiconductor device with trench-type element isolation structure 未知
公开(公告)号：DE19750378A1
公开(公告)日：1998-10-15
申请号：DE19750378
申请日：1997-11-13
申请人： MITSUBISHI ELECTRIC CORP
发明人： KUROI TAKASHI , HORITA KATSUYUKI , SAKAI MAIKO , INOUE YASUO
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8242 , H01L27/108
摘要： The semiconductor device has a semiconductor substrate (1) provided with an alignment marking region (11A), having at least one trench (10A) in the substrate surface and an element formation region (11B,11C) with an element isolation film (2B,2C), for isolating a number of semiconductor elements, filling further trenches (10B,10C) formed in the substrate surface. The first trench is used for an alignment marking provided by an embedded silicon oxide film (2A), with its surface recessed relative to the surface of the semiconductor substrate, to provide a level difference in the substrate surface at the alignment marking.

8. 发明专利

DE4224793C2 未知
公开(公告)号：DE4224793C2
公开(公告)日：1998-07-09
申请号：DE4224793
申请日：1992-07-27
申请人： MITSUBISHI ELECTRIC CORP
发明人： INOUE YASUO , NISHIMURA TADASHI , ASHIDA MOTOI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786
摘要： An upper insulating layer is formed on an upper surface of a gate electrode formed on an insulating substrate. A gate insulating layer is formed on sidewalls of the gate electrode and the surfaces of the upper insulating layer. A semiconductor layer is formed on the surfaces of the gate insulating layer. Three source/drain regions are formed in the semiconductor layer. Two independent channel regions are formed in the semiconductor layer along both side surfaces of the gate electrode. Source/drain regions are arranged on both ends of two channel regions. Each source/drain region has an LDD structure formed in a self alignment manner by an oblique ion implantation method and a vertical ion implantation method using sidewall insulating layers formed on the channel regions as masks.

9. 发明专利

FR2746963A1 未知
公开(公告)号：FR2746963A1
公开(公告)日：1997-10-03
申请号：FR9615155
申请日：1996-12-10
申请人： MITSUBISHI ELECTRIC CORP
发明人： YAMAGUCHI YASUO , SATO HIROTOSHI , INOUE YASUO , IWAMATSU TOSHIAKI
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L29/786 , H01L23/60 , H02H3/22
摘要： An I/O protection circuit includes a P-channel MOS transistor connected between an input terminal and a power supply line, and an N-channel MOS transistor connected between the input terminal and a ground line. Gate electrodes of both the transistors are floated. The transistors may be replaced with gate diodes. Further, gate electrodes may be formed from the same layer as a gate electrode provided for field shielding.

10. 发明专利

DE19651247C2 未知
公开(公告)号：DE19651247C2
公开(公告)日：2002-01-10
申请号：DE19651247
申请日：1996-12-10
申请人： MITSUBISHI ELECTRIC CORP
发明人： YAMAGUCHI YASUO , SATO HIROTOSHI , INOUE YASUO , IWAMATSU TOSHIAKI
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L29/786 , H01L23/60
摘要： An I/O protection circuit includes a P-channel MOS transistor connected between an input terminal and a power supply line, and an N-channel MOS transistor connected between the input terminal and a ground line. Gate electrodes of both the transistors are floated. The transistors may be replaced with gate diodes. Further, gate electrodes may be formed from the same layer as a gate electrode provided for field shielding.

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