专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

DE3725822A1 未知
公开(公告)号：DE3725822A1
公开(公告)日：1988-02-18
申请号：DE3725822
申请日：1987-08-04
申请人： MITSUBISHI ELECTRIC CORP
发明人： KISHIDA SATORU , SAKASHITA KAZUHIRO , HANIBUCHI TOSHIAKI , TOMIOKA ICHIRO , ARAKAWA TAKAHIKO
IPC分类号： G06F11/16 , G01R31/3185 , G06F11/22 , G11C29/00 , H01L27/06 , G01R31/26
摘要： A semiconductor integrated circuit device for transmitting data between a plurality of circuit blocks at least one thereof including a sequential circuit and enabling the circuit blocks to test in a scan testing type which has a plurality of scan registers provided between the plurality of circuit blocks corresponding to the number of bits of data to be transmitted for outputting the output data of the previous stage circuit block as it is at ordinary operating time and for holding and outputting the output data of the previous circuit block or test data for scan test synchronously with an external clock at testing time so that the circuits are connected by a shift register pass in such a manner that the entirety has one shaft register function, and a latch circuit provided at its data input terminal to the data output terminal of the corresponding scan register for outputtting the output data of the corresponding scan register as it is to the circuit block of next stage at ordinary operation time and holding the output data of the corresponding scan register before the scanning operation in a scan mode at testing time to continuously apply the data to the circuit block of next stage and holding and outputting the output data of the corresponding scan register in a test mode synchronously with the external clock, test data setting means for setting serial data of test from the exterior of the circuit device to each of the scan registers, test result outputting means for sequentially outputting the data of each scan register as serial data out of the circuit device, and operation switching means for switching the ordinary operation and the testing operation and switching the scan mode and the test mode, thereby enabling the semiconductor integrated circuit device to be readily subjected to a scan test together with circuit blocks including asynchronous sequential circuits.

2. 发明专利

DE3722615A1 未知
公开(公告)号：DE3722615A1
公开(公告)日：1988-02-18
申请号：DE3722615
申请日：1987-07-06
申请人： MITSUBISHI ELECTRIC CORP
发明人： SAKASHITA KAZUHIRO , KISHIDA SATORU , HANIBUCHI TOSHIAKI , TOMIOKA ICHIRO , ARAKAWA TAKAHIKO
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , G01R31/26 , H01L27/04
摘要： A test circuit of a semiconductor integrated circuit apparatus comprising a latch circuit connected to an output terminal of a scan register for holding output data of the scan register stored before scanning in a scan mode during the test operation.

3. 发明专利

DE3447345A1 Integrated semiconductor circuit arrangement 未知
公开(公告)号：DE3447345A1
公开(公告)日：1985-07-11
申请号：DE3447345
申请日：1984-12-24
申请人： MITSUBISHI ELECTRIC CORP
发明人： ARAKAWA TAKAHIKO
IPC分类号： H01L21/60 , H01L23/498 , H01L21/88
摘要： An integrated semiconductor circuit arrangement contains:… A plurality of terminal areas 23, 26 which are arranged along one edge of a semiconductor chip 21, a plurality of external connecting elements 24, 27 which are provided for connection to a first group of terminal areas which are selected from the totality of terminal areas, the first external connecting elements 24 being arranged on a first arrangement line AL 1 in parallel with the first terminal areas 23, maintaining the same intermediate spaces as the first terminal areas 23; a plurality of second external connecting elements 27 which are intended for connection to the second terminal areas 26, the second external connecting elements 27 being arranged on a second arrangement line AL 2 in parallel with the second terminal areas 26 and maintain between them the same intermediate spaces as the second terminal areas 26; each of the said first terminal areas 23 is arranged at minimum distance from the in each case associated first connecting element 24, each of the second terminal areas 26 is arranged at a minimum distance from the in each case associated second external connecting element 27. … …

4. 发明专利

DE3900536A1 未知
公开(公告)号：DE3900536A1
公开(公告)日：1990-06-07
申请号：DE3900536
申请日：1989-01-10
申请人： MITSUBISHI ELECTRIC CORP
发明人： ARAKAWA TAKAHIKO , SAKASHITA KAZUHIRO , KISHIDA SATORU , HANIBUCHI TOSHIAKI , TOMIOKA ICHIRO , UEDA MASAHIRO , OKUNO YOSHIHIRO
IPC分类号： H01L21/82 , H01L27/118
摘要： An internal logic gate portion (3) is provided in the central portion of a semiconductor chip (1), input/output buffers (4) are provided to surround the internal logic gate portion (3), and bonding pads (2) are provided in the peripheral portions of the semiconductor chip (1) corresponding to input/output buffer cells (5) in the input/output buffer. Each of the input/output buffer cells (5) comprises an output P-MOS portion (6), an output N-MOS portion (7), an input/logic P-MOS portion (8) and an input/logic N-MOS portion (9), which are respectively arranged in a single line in the direction from the bonding pads (2) to the internal logic gate portion (3). In the above described structure, the size of each of the input/output buffer cells (5) in the pad arranging direction of the bonding pads (2) is decreased, so that the number of input/output pins can be increased according to the decreased use of space in the pad arranging direction required by each input/output buffer cell (5).

5. 发明专利

FR2557366A1 Integrated circuit semiconductor connection pattern 未知
公开(公告)号：FR2557366A1
公开(公告)日：1985-06-28
申请号：FR8419816
申请日：1984-12-26
申请人： MITSUBISHI ELECTRIC CORP
发明人： ARAKAWA TAKAHIKO
IPC分类号： H01L21/60 , H01L23/498 , H01L23/50
摘要： A set of connections is formed between an edge of a semiconductor chip by using a line of bonding pads along the edge, each connected by a conductor to an external lead extending from a housing element. All the bridging conductors are parallel for space saving. To form the required number of connections, the conductors are connected to two lines of connecting leads, one row being further out than the other. The two lines are parallel and the bonding pads are connected alternately to the inner and outer rows.

6. 发明专利

DE3837080A1 未知
公开(公告)号：DE3837080A1
公开(公告)日：1989-05-11
申请号：DE3837080
申请日：1988-10-31
申请人： MITSUBISHI ELECTRIC CORP
发明人： TOMIOKA ICHIRO , UEDA MASAHIRO , ARAKAWA TAKAHIKO , HANIBUCHI TOSHIAKI , OKUNO YOSHIHIRO
IPC分类号： G01R19/165 , G01R31/316 , G01R31/317 , G01R31/319 , H03K17/00 , H03K17/16 , H03K19/003 , H03K19/0948
摘要： An inverter circuit (I3) is disclosed which includes a P-channel MOSFET (3) and a N-channel MOSFET (4) connected in series between a power supply (VDD) and a ground (GND). The inverter circuit further includes a P-channel MOSFET (5) and a N-channel MOSFET (6) connected in parallel between the gates of the FETs (3) and (4). The FETs (3) and (4) have their gates connected to receive testing mode signals (TE). In a testing mode operation, the FET (6) is rendered conductive to allow an input signal to be applied to the gate of the FET (4) through the FET (6). The FET (4), having an on-resistance lower than the FET (3), is driven into conduction in response to the output signal applied through the FET (6), thereby providing a slowly rising output signal. The slow rising output signal is free from undershoot or ringing.

7. 发明专利

DE3725823A1 未知
公开(公告)号：DE3725823A1
公开(公告)日：1988-02-18
申请号：DE3725823
申请日：1987-08-04
申请人： MITSUBISHI ELECTRIC CORP
发明人： HANIBUCHI TOSHIAKI , TOMIOKA ICHIRO , SAKASHITA KAZUHIRO , KISHIDA SATORU , ARAKAWA TAKAHIKO
IPC分类号： G01R31/3185 , G01R31/28
摘要： A semiconductor integrated circuit includes cascaded asynchronous sequential logic circuits. Scanning shift registers are provided between the asynchronous sequential circuits to permit test data to be applied to the inputs of the circuits and to latch and shift out output data provided by the circuits in response to the test data. Additional gating circuitry is provided between the scanning shift registers and the inputs of the asynchronous sequential circuits to prevent new data latched into the scanning shift register from causing the asynchronous sequential circuit connected to the scanning shift register output from changing state during testing. This same additional circuitry may be used to provide pulses of controlled width and/or timing to asynchronous sequential circuit inputs in response to externally generated gating control signals.

8. 发明专利

DE3725821A1 未知
公开(公告)号：DE3725821A1
公开(公告)日：1988-02-18
申请号：DE3725821
申请日：1987-08-04
申请人： MITSUBISHI ELECTRIC CORP
发明人： SAKASHITA KAZUHIRO , KISHIDA SATORU , HANIBUCHI TOSHIAKI , TOMIOKA ICHIRO , ARAKAWA TAKAHIKO
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , G11C19/28 , G11C29/00 , H01L27/06
摘要： A semiconductor integrated circuit device includes a plurality of latch circuits which are provided between adjacent circuit blocks. Each latch circuit functions to transfer output data from a preceding circuit block directly to a subsequent circuit block during a normal operation of the circuit device, to hold the output data until a scanning of associated scan register and supply them to the subsequent circuit block in a scan mode of a test operation and to hole the output data while outputting them in synchronism with an external clock in a test mode of the test operation.

9. 发明专利

DE4103570A1 Integrated semiconductor circuit on semiconductor substrate - has clock pulse signal driver formed in third region adjacent to pair of coupling faces 未知
公开(公告)号：DE4103570A1
公开(公告)日：1991-08-08
申请号：DE4103570
申请日：1991-02-06
申请人： MITSUBISHI ELECTRIC CORP
发明人： ARAKAWA TAKAHIKO
IPC分类号： H01L21/82 , H01L27/118
摘要： The integrated circuit on a semiconductor substrate has a gate field and a reduced shift of the clock pulse signals. It has a clock pulse signal driver, formed in a part under an energy supply terminal for an input-output buffer in an energy supply region (53), or an earth coupling region (54). The clock pulse signal driver is formed in the energy supply coupling region, contrary to the conventional design. Thus it can be of sufficient size to provide clock pulse signals for each base cell column (4). In this arrangement the input output buffer is not engaged unnecessarily by the clock pulse signal driver. The connecting terminal faces are well utilised. ADVANTAGE - Facility for control of clock pulse offset and noise effects, without reduction of the number of input and output pins.

10. 发明专利

FR2557366B1 未知
公开(公告)号：FR2557366B1
公开(公告)日：1988-10-14
申请号：FR8419816
申请日：1984-12-26
申请人： MITSUBISHI ELECTRIC CORP
发明人： ARAKAWA TAKAHIKO
IPC分类号： H01L21/60 , H01L23/498 , H01L23/50

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式