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1. 发明申请

WO2016003820A2 SYSTEM AND METHODS FOR EXPANDABLY WIDE OPERAND INSTRUCTIONS 审中-公开
标题翻译：用于扩展操作和指令的系统和方法
公开(公告)号：WO2016003820A2
公开(公告)日：2016-01-07
申请号：PCT/US2015038078
申请日：2015-06-26
申请人： MICROUNITY SYSTEMS ENG
发明人： HANSEN CRAIG , MOUSSOURIS JOHN , MASSALIN ALEXIA
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F12/0875 , G06F9/3016 , G06F9/30181 , G06F9/30192 , G06F9/34 , G06F9/3824 , G06F9/3895 , G06F2212/452
摘要： Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.
摘要翻译：公开了可扩展的宽操作，其中操作数比处理器和存储器之间的数据路径宽，用于执行指令。可扩展的宽操作数减少了在执行计算的功能单元的设计中相关处理器的特性的影响，包括寄存器文件的宽度，处理器时钟速率，处理器的异常子系统和负载中的操作序列并在宽缓存中使用操作数。

2. 发明申请

WO2016003820A3 SYSTEM AND METHODS FOR EXPANDABLY WIDE OPERAND INSTRUCTIONS 审中-公开
标题翻译：用于宽泛操作说明的系统和方法
公开(公告)号：WO2016003820A3
公开(公告)日：2016-03-17
申请号：PCT/US2015038078
申请日：2015-06-26
申请人： MICROUNITY SYSTEMS ENG
发明人： HANSEN CRAIG , MOUSSOURIS JOHN , MASSALIN ALEXIA
IPC分类号： G06F9/30
CPC分类号： G06F12/0875 , G06F9/3016 , G06F9/30181 , G06F9/30192 , G06F9/34 , G06F9/3824 , G06F9/3895 , G06F2212/452
摘要： Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.
摘要翻译：公开了可扩展地广泛的操作，其中在执行指令中使用比处理器和存储器之间的数据路径更宽的操作数。可扩展的宽操作数减少了执行计算的功能单元的设计中相关处理器的特性的影响，包括寄存器文件的宽度，处理器时钟速率，处理器的异常子系统以及加载中的操作顺序并在宽缓存中使用操作数。

3. 发明申请

WO0023875A8 SYSTEM WITH WIDE OPERAND ARCHITECTURE, AND METHOD 审中-公开
标题翻译：具有宽操作体系结构的系统和方法
公开(公告)号：WO0023875A8
公开(公告)日：2001-06-07
申请号：PCT/US9919342
申请日：1999-08-24
申请人： MICROUNITY SYSTEMS ENG , HANSEN CRAIG , MOUSSOURIS JOHN
发明人： HANSEN CRAIG , MOUSSOURIS JOHN
IPC分类号： G06F9/38 , G06F7/38 , G06F7/48 , G06F7/483 , G06F7/499 , G06F7/52 , G06F7/76 , G06F9/30 , G06F9/302 , G06F9/315 , G06F9/318 , G06F9/34
CPC分类号： G06F9/30014 , G06F7/483 , G06F7/4991 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30101 , G06F9/30112 , G06F9/30167 , G06F9/3017 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3885
摘要： A general purpose processor with four copies of an access unit, with an access instruction fetch queue A-queue (101-104). Each A-queue (101-104) is coupled to an access register file AR (105-108) which is coupled to two access functional units A (109-116). In a typical embodiment, each thread of the processor may have on the order of sixty-four general purpose registers. The access unit functions independently for four simultaneous threads of execution, and each compute control flow by performing arithmetic and branch instructions and access memory by performing load and store instructions. These access units also provide wide specifiers for wide operand instructions. These eight access functional units A (109-116) produce results for access register files (105-108) and memory addresses to a shared memory system (117-120).
摘要翻译：具有访问单元的四个副本的通用处理器，具有访问指令获取队列A队列（101-104）。每个A队列（101-104）耦合到耦合到两个访问功能单元A（109-116）的访问寄存器文件AR（105-108）。在典型的实施例中，处理器的每个线程可以具有六十四个通用寄存器的数量级。访问单元独立地为四个同时执行的线程独立地起作用，并且通过执行加载和存储指令来执行算术和分支指令和访问存储器来执行每个计算控制流程。这些访问单元还提供广泛的说明符，用于广泛的操作数指令。这八个访问功能单元A（109-116）产生访问寄存器文件（105-108）和存储器地址到共享存储器系统（117-120）的结果。

4. 发明申请

WO2005008410A2 PROGRAMMABLE PROCESSOR AND METHOD WITH WIDE OPERATIONS 审中-公开
标题翻译：具有广泛操作的可编程处理器和方法
公开(公告)号：WO2005008410A2
公开(公告)日：2005-01-27
申请号：PCT/US2004022126
申请日：2004-07-12
申请人： MICROUNITY SYSTEMS ENG
发明人： HANSEN CRAIG , MOUSSOURIS JOHN , MASSALIN ALEXIA
IPC分类号： G06F20060101 , G06F12/00 , G06F17/50 , G06F
CPC分类号： G06F9/3001 , G03F1/36 , G06F9/30 , G06F9/30007 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30098 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/35 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4425 , G06F9/45533 , G06F12/02 , G06F17/5068 , G06F17/5072 , G06F17/5081 , G06F2217/12 , H03M13/158 , H03M13/4169 , Y02D10/13 , Y02D10/26 , Y02D10/28 , Y02P90/265
摘要： A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
摘要翻译：一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展为大于通用寄存器或数据路径宽度的宽度来改善处理器的性能。本发明通过使用通用寄存器的内容来提供实质上大于处理器的数据路径宽度的操作数，以指定可以读取或写入多个数据路径宽度的存储器地址，以及操作数的大小和形状。另外，描述了用于实现这些指令的若干指令和装置，如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优势。

5. 发明专利

AT532130T 未知
公开(公告)号：AT532130T
公开(公告)日：2011-11-15
申请号：AT07111352
申请日：1996-08-16
申请人： MICROUNITY SYSTEMS ENG
发明人： HANSEN CRAIG , MOUSSOURIS JOHN
IPC分类号： G06F9/30 , G06F9/302 , G06F9/308 , G06F9/312 , G06F9/315 , G06F9/38 , G06F12/08 , G06F12/10 , G06F15/76 , G06F15/78 , H04N5/00 , H04N7/24

6. 发明公开

EP1652090A4 PROGRAMMABLE PROCESSOR AND METHOD WITH WIDE OPERATIONS 审中-公开
标题翻译： VERFAHREN MIT BREITENOPERATIONEN的PROGRAMMIERBARER PROZESSOR
公开(公告)号：EP1652090A4
公开(公告)日：2008-04-09
申请号：EP04756853
申请日：2004-07-12
申请人： MICROUNITY SYSTEMS ENG
发明人： HANSEN CRAIG , MOUSSOURIS JOHN , MASSALIN ALEXIA
IPC分类号： G06F12/00 , G06F20060101 , G06F17/50
CPC分类号： G06F9/3001 , G03F1/36 , G06F9/30 , G06F9/30007 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30098 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/35 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4425 , G06F9/45533 , G06F12/02 , G06F17/5068 , G06F17/5072 , G06F17/5081 , G06F2217/12 , H03M13/158 , H03M13/4169 , Y02D10/13 , Y02D10/26 , Y02D10/28 , Y02P90/265
摘要： A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width accessible number of general purpose registers.
摘要翻译：一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且通过使用通用寄存器的内容来显着地大于处理器的数据路径宽度的操作数，以及操作数的大小和形状。此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度可访问数量，则获得性能优点。

7. 发明公开

EP0845120A4 GENERAL PURPOSE, PROGRAMMABLE MEDIA PROCESSOR 失效
标题翻译：通用可编程媒体处理器
公开(公告)号：EP0845120A4
公开(公告)日：2005-05-04
申请号：EP96928129
申请日：1996-08-16
申请人： MICROUNITY SYSTEMS ENG
发明人： HANSEN CRAIG , MOUSSOURIS JOHN
IPC分类号： G06F9/30 , G06F9/302 , G06F9/308 , G06F9/312 , G06F9/315 , G06F9/38 , G06F12/08 , G06F12/10 , G06F15/78 , H04N5/00 , H04N7/24 , G06F7/00 , G06F7/38
CPC分类号： G06F9/3802 , G06F9/30 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30072 , G06F9/30087 , G06F9/30145 , G06F9/3867 , G06F9/3869 , G06F12/0875 , G06F12/1027 , G06F15/7832 , G06F15/7842 , G06F2212/2515 , H04N21/2365 , H04N21/238 , H04N21/23805 , H04N21/4347 , Y02D10/13
摘要： A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data through out of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120) are provided. The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.

8. 发明公开

EP3161616A4 SYSTEM AND METHODS FOR EXPANDABLY WIDE OPERAND INSTRUCTIONS 审中-公开
公开(公告)号：EP3161616A4
公开(公告)日：2017-12-27
申请号：EP15815691
申请日：2015-06-26
申请人： MICROUNITY SYSTEMS ENG INC
发明人： HANSEN CRAIG , MOUSSOURIS JOHN , MASSALIN ALEXIA
IPC分类号： G06F9/30 , G06F9/34 , G06F9/38 , G06F12/0875
CPC分类号： G06F12/0875 , G06F9/3016 , G06F9/30181 , G06F9/30192 , G06F9/34 , G06F9/3824 , G06F9/3895 , G06F2212/452
摘要： Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.

9. 发明公开

EP1236090A4 SYSTEM AND METHOD TO IMPLEMENT A CROSS-BAR SWITCH OF A BROADBAND PROCESSOR 审中-公开
标题翻译： SYSTEM UND VERFAHREN ZUM IMPLEMENTIER EINES CROSS-BARSCHTERTER EINES BREITBANDPROZESSORS
公开(公告)号：EP1236090A4
公开(公告)日：2002-09-04
申请号：EP00910150
申请日：2000-02-11
申请人： MICROUNITY SYSTEMS ENG
发明人： HANSEN CRAIG , BATEMAN BRUCE , MOUSSOURIS JOHN
IPC分类号： G06F7/76 , G06F9/308 , G06F9/30
CPC分类号： G06F7/76 , G06F9/30018
摘要： The present invention provides a cross-bar circuit (100) that implements a switch (115) of a broadband processor. The cross-bar circuit (100) includes: a switch circuit (115) which includes 2 .2 :1 multiplexor circuits (202-204) where each of the 2 :1 multiplexor circuits (202-204) has a unique n-bit index input, one disable input, and a 2 -bit wide source input receives an n-bit index at the n-bit index input, a disable bit at the disable input, and the 2 -bit input source word at the 2 -bit wide source input, and decodes the n-bit index either to select and output as an output destination bit one bit from the 2 -bit input source word if the disable bit has a logic low value; a cache memory (110) that has 2 cache datapath inputs; and 2 cache index input; and a control circuit (105) that has a plurality of control inputs receives the partially decoded instruction information on the plurality of control inputs, provides a second set of the n-bit indexes for the switch circuit (115), and provides the disable bits for the switch circuit (115) where the control circuit (105) is logically coupled to the switch circuit (115) and to the cache memory (110).
摘要翻译：本发明提供了一种实现宽带处理器的开关（115）的交叉开关电路（100）。交叉开关电路（100）包括：包括2.2:1多路复用器电路（202-204）的开关电路（115），其中2:1多路复用器电路（202-204）中的每一个具有唯一的n位索引输入，一个禁止输入和一个2位宽的源输入在n位索引输入处接收n位索引，在禁用输入处接收禁用位，以及在2位宽信号源处接收2位输入源字输入，并对n位索引进行解码，以便如果禁用位具有逻辑低值，则从2位输入源字中选择并作为输出目的位输出一位; 高速缓冲存储器（110），其具有2个高速缓存数据路径输入; 和2个缓存索引输入; 并且具有多个控制输入的控制电路（105）接收关于所述多个控制输入的所述部分解码的指令信息，为所述开关电路（115）提供第二组n位索引，并将所述禁用位对于其中控制电路（105）逻辑地耦合到开关电路（115）和高速缓冲存储器（110）的开关电路（115）。

10. 发明专利

AT528712T 未知
公开(公告)号：AT528712T
公开(公告)日：2011-10-15
申请号：AT07111351
申请日：1996-08-16
申请人： MICROUNITY SYSTEMS ENG
发明人： HANSEN CRAIG , MOUSSOURIS JOHN
IPC分类号： G06F9/30 , G06F9/302 , G06F9/308 , G06F9/312 , G06F9/315 , G06F9/38 , G06F12/08 , G06F12/10 , G06F15/76 , G06F15/78 , H04N5/00 , H04N7/24

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