会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明申请
    • APPARATUS AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY
    • 修复半导体存储器的装置和方法
    • WO2007005218B1
    • 2007-04-26
    • PCT/US2006023219
    • 2006-06-14
    • MICRON TECHNOLOGY INCMARTIN CHRIS GMANNING TROY AKEETH BRENT
    • MARTIN CHRIS GMANNING TROY AKEETH BRENT
    • G11C29/00
    • G11C17/165G11C29/4401G11C29/789G11C29/802G11C29/808G11C2029/4402
    • An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.
    • 一种用于修复半导体存储器件的装置和方法包括第一存储器单元阵列,第一冗余单元阵列和修复电路,该修复电路被配置为非易失性地将指定至少一个故障存储器单元的第一地址存储在第一存储器单元阵列中。 第一易失性高速缓存存储对应于指定至少一个有缺陷的存储单元的第一地址的第一高速缓存地址。 修复电路将指定第一存储单元阵列的至少一个故障存储单元的第一地址分配给第一易失性缓存。 当第一存储器访问对应于第一高速缓存地址时,匹配电路将来自第一冗余单元阵列的至少一个冗余存储器单元替换为第一存储器单元阵列中的至少一个有缺陷存储器单元。
    • 7. 发明申请
    • MEMORY SYSTEM AND METHOD FOR STROBING DATA, COMMAND AND ADDRESS SIGNALS
    • 存储器系统和数据,命令和地址信号的方法
    • WO2006026526A3
    • 2006-05-04
    • PCT/US2005030593
    • 2005-08-26
    • MICRON TECHNOLOGY INCLIN FENGKEETH BRENTJOHNSON BRIANLEE SEONG-HOON
    • LIN FENGKEETH BRENTJOHNSON BRIANLEE SEONG-HOON
    • H04L7/00G06F12/16
    • G11C7/109G11C7/1006G11C7/1078G11C7/1087G11C7/22G11C7/222
    • A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.
    • 存储器系统将来自存储器控制器的命令,地址或写入数据信号耦合到存储器设备,并将数据信号从存储器设备读取到存储器控制器。 存储器控制器和存储器设备中的每一个中的相应选通脉冲发生器电路均产生同相选通信号和正交选通信号。 存储在存储器控制器中的各个输出锁存器中的命令,地址或写入数据信号由来自内部选通脉冲发生器电路的同相信号计时。 这些命令,地址或写入数据信号被从存储器控制器耦合到存储器装置的正交选通信号锁存到存储器装置中的输入锁存器中。 以基本上相同的方式,使用内部选通脉冲发生器电路产生的同相和正交选通信号将读取数据信号从存储器装置耦合到存储器控制器。