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1. 发明申请

WO2011031534A1 THERMALLY SHIELDED RESISTIVE MEMORY ELEMENT FOR LOW PROGRAMMING CURRENT 审中-公开
标题翻译：用于低编程电流的热屏蔽电阻记忆元件
公开(公告)号：WO2011031534A1
公开(公告)日：2011-03-17
申请号：PCT/US2010/046892
申请日：2010-08-27
申请人： MICRON TECHNOLOGY, INC. , SANDHU, Gurtej , SMYTHE, John , LIU, Jun
发明人： SANDHU, Gurtej , SMYTHE, John , LIU, Jun
IPC分类号： G11C13/02 , G11C16/02 , H01L45/00
CPC分类号： H01L45/06 , G11C13/0004 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： Various embodiments described herein provide a memory device including a variable resistance material (210) having a thermally isolating and electrically conductive isolation region (270, 280) arranged between the variable resistance material and an electrode (220 or 230) to allow for efficient heating of the variable resistance material by a programming current. An electrically and thermally isolating isolation region (260) may be arranged around the variable resistance material.
摘要翻译：本文所述的各种实施例提供了一种存储器件，其包括具有布置在可变电阻材料和电极（220或230）之间的热隔离和导电隔离区域（270,280）的可变电阻材料（210），以允许有效加热可变电阻材料通过编程电流。电隔离隔离区（260）可以围绕可变电阻材料布置。

2. 发明申请

WO2010039424A1 UNIDIRECTIONAL SPIN TORQUE TRANSFER MAGNETIC MEMORY CELL STRUCTURE 审中-公开
标题翻译：单向转子扭矩传递磁性记忆体结构
公开(公告)号：WO2010039424A1
公开(公告)日：2010-04-08
申请号：PCT/US2009/057008
申请日：2009-09-15
申请人： MICRON TECHNOLOGY, INC. , LIU, Jun , SANDHU, Gurtej
发明人： LIU, Jun , SANDHU, Gurtej
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/161 , G11C11/1695 , H01L43/02
摘要： Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells (50) having two pinned layers (102, 110, 216, 224, 310, 354, 366, 408, 416, 464, 472, 502, 510, 566, 574) and a free layer (106, 220, 358, 362, 412, 468, 506, 570) therebetween. By utilizing two pinned layers (102, 110, 216, 224, 310, 354, 366, 408, 416, 464, 472, 502, 510, 566, 574), the spin torque effect on the free layer (106, 220, 358, 362, 412, 468, 506, 570) from each of the two pinned layers (102, 110, 216, 224, 310, 354, 366, 408, 416, 464, 472, 502, 510, 566, 574), respectively, allows the memory cells (50) to be programmed with unidirectional currents.
摘要翻译：配置为单向编程的自旋扭矩传递磁性随机存取存储器件以及编程这种器件的方法。这些装置包括具有两个被钉扎层（102,110,216,224,310,354,366,408,416,446,472,502,510,566,574）的存储单元（50）和自由层（106， 220,358,362,412,468,506,570）。通过利用两个固定层（102,110,216,224,310,354,366,408,416,446,472,502,510,566,574），对自由层（106,220，（102,110,216,224,310,454,366,408,416,446,472,504,510,566,574）中的每一个上的两个固定层（358,362,412,468,506,570）中的每一个，分别允许存储单元（50）用单向电流编程。

3. 发明申请

WO2010039422A1 STT-MRAM CELL STRUCTURE INCORPORATING PIEZOELECTRIC STRESS MATERIAL 审中-公开
标题翻译： STT-MRAM细胞结构掺杂压电材料
公开(公告)号：WO2010039422A1
公开(公告)日：2010-04-08
申请号：PCT/US2009/057005
申请日：2009-09-15
申请人： MICRON TECHNOLOGY, INC. , LIU, Jun , KRAMER, Steve , SANDHU, Gurtej
发明人： LIU, Jun , KRAMER, Steve , SANDHU, Gurtej
IPC分类号： G11C11/16
CPC分类号： G11C11/161 , G11C11/16 , G11C11/1675 , H01L27/228 , H01L43/08
摘要： A magnetic memory cell (104, 106, 108) including a piezoelectric material (102), and methods of operating the memory cell are provided. The memory cell includes a stack, and the piezoelectric material may be formed as a layer in the stack or adjacent the layers of the cell stack. The piezoelectric material may be used to induce a transient stress during programming of the memory cell to reduce the critical switching current of the memory cell.
摘要翻译：提供了包括压电材料（102）的磁存储单元（104,106,108）以及操作存储单元的方法。存储单元包括堆叠，并且压电材料可以形成为堆叠中的层或邻近电池堆的层。压电材料可以用于在编程存储器单元期间引起瞬态应力，以减小存储单元的临界开关电流。

4. 发明申请

WO2010053713A1 SPIN TORQUE TRANSFER CELL STRUCTURE UTILIZING FIELD-INDUCED ANTIFERROMAGNETIC OR FERROMAGNETIC COUPLING 审中-公开
标题翻译：旋转扭转细胞结构利用场诱导的抗血管病变或FERROMAGNETIC联合
公开(公告)号：WO2010053713A1
公开(公告)日：2010-05-14
申请号：PCT/US2009/061647
申请日：2009-10-22
申请人： MICRON TECHNOLOGY, INC. , LIU, Jun , SANDHU, Gurtej
发明人： LIU, Jun , SANDHU, Gurtej
IPC分类号： G11C11/16 , G01R33/09 , H01F10/32 , H04L27/156
CPC分类号： H01F10/329 , B82Y25/00 , G01R33/093 , G01R33/1284 , G11C11/161 , G11C11/1675 , H01F10/3254 , H01F10/3268
摘要： A magnetic memory cell (50) including a soft magnetic layer (104, 204, 254, 304, 354) and a coupling layer (106, 206, 256, 306, 356), and methods of operating the memory cell (50) are provided. The memory cell (50) includes a stack (52, 100, 200, 250, 300, 350) with a free ferromagnetic layer (108, 208, 258, 308, 358) and a pinned ferromagnetic layer (112, 212, 262, 312, 362), and a soft magnetic layer (104, 204, 254, 304, 354) and a coupling layer (106, 206, 256, 306, 356) may also be formed as layers in the stack (52, 100, 200, 250, 300, 350). The coupling layer (106, 206, 256, 306, 356) may cause antiferromagnetic coupling to induce the free ferromagnetic layer (108, 208, 258, 308, 358) to be magnetized in a direction antiparallel to the magnetization of the soft magnetic layer (104, 204, 254, 304, 354), or the coupling layer (106, 206, 256, 306, 356) may cause ferromagnetic coupling to induce the free ferromagnetic layer (108, 208, 258, 308, 358) to be magnetized in a direction parallel to the magnetization of the soft magnetic layer (104, 204, 254, 304, 354).
摘要翻译：包括软磁层（104,204,254,304,354）和耦合层（106,206,256,306,356）的磁存储单元（50）和操作存储单元（50）的方法是提供。存储单元（50）包括具有自由铁磁层（108,208,258,308,358）和钉扎铁磁层（112,212,262,312）的堆叠（52,100,200,250,300,350） 312,262,362），并且软磁层（104,204,254,304,354）和耦合层（106,206,256,306,356）也可以形成为层叠在层叠体（52,100） 200,250,300,350）。耦合层（106,206,256,306,356）可以引起反铁磁耦合以使自由铁磁层（108,208,258,308,358）在与软磁层的磁化方向反平行的方向上被磁化（104,204,254,304,354）或耦合层（106,206,256,306,356）可以引起铁磁耦合以将游离铁磁性层（108,208,258,308,358）引导为在与软磁性层（104,204,254,304,354）的磁化平行的方向上磁化。

5. 发明申请

WO2012138484A1 CONFINED MAGNETIC MEMORY CELL STRUCTURES AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：限制磁记忆体细胞结构及其形成方法
公开(公告)号：WO2012138484A1
公开(公告)日：2012-10-11
申请号：PCT/US2012/030191
申请日：2012-03-22
申请人： MICRON TECHNOLOGY, INC. , LIU, Jun , SANDHU, Gurtej
发明人： LIU, Jun , SANDHU, Gurtej
IPC分类号： H01L43/08 , H01L43/12
CPC分类号： H01L43/08 , G11C11/161 , H01L43/02 , H01L43/10 , H01L43/12
摘要： Techniques for reducing etch damage in magnetic memory cells are provided. Memory cell structures are typically formed using dry etch and/or planarization processes which damage certain regions of the memory cell structure. For example, the free magnetic region in magnetic memory cell structures may be susceptible to demagnetization. Such regions may be substantially confined by barrier materials during the formation of the memory cell structure, such that the edges of such regions are protected from damaging processes. A memory cell structure is formed and confined within a recess in dielectric material by means of a damascene - type manufacturing process: a bottom lead (22) is recessed in a dielectric (26) and the layers (20, 18, 16, 14) of the magnetic memory cell are formed in the recess; CMP is carried out to remove material outside the recess.
摘要翻译：提供了用于减小磁存储器单元中的蚀刻损伤的技术。通常使用破坏存储单元结构的某些区域的干蚀刻和/或平坦化处理来形成存储单元结构。例如，磁存储单元结构中的自由磁区可能易于退磁。这样的区域在形成存储单元结构期间可以基本上被阻挡材料限制，使得这些区域的边缘被保护免受损坏的过程。存储单元结构通过镶嵌型制造工艺形成并限制在电介质材料的凹槽内;底部引线（22）凹陷在电介质（26）中，层（20,18,16,14）在所述凹部中形成所述磁存储单元; 进行CMP以去除凹部外部的材料。

6. 发明申请

WO2010080510A1 STT-MRAM CELL STRUCTURES 审中-公开
标题翻译： STT-MRAM细胞结构
公开(公告)号：WO2010080510A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/068511
申请日：2009-12-17
申请人： MICRON TECHNOLOGY, INC. , LIU, Jun , SANDHU, Gurtej
发明人： LIU, Jun , SANDHU, Gurtej
IPC分类号： G11C11/15 , G11C11/16
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/161 , G11C11/1659 , H01L29/66007 , H01L43/02 , H01L43/08 , H01L43/12
摘要： A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.
摘要翻译：提供包括非磁性桥的磁性单元结构以及制造该结构的方法。磁性电池结构包括自由层，钉扎层和电连接自由层和钉扎层的非磁性桥。非磁性桥的形状和/或构造使编程电流通过磁性单元结构，使得结构自由层中编程电流的横截面面积小于结构的横截面。自由层中编程电流的横截面积的减小使编程电流能够达到自由层中的关键开关电流密度并切换自由层的磁化，对磁性单元进行编程。

7. 发明申请

WO2010039423A1 SPIN CURRENT GENERATOR FOR STT-MRAM OR OTHER SPINTRONICS APPLICATIONS 审中-公开
标题翻译：用于STT-MRAM或其他SPINTRONICS应用的旋转电流发生器
公开(公告)号：WO2010039423A1
公开(公告)日：2010-04-08
申请号：PCT/US2009/057006
申请日：2009-09-15
申请人： MICRON TECHNOLOGY, INC. , LIU, Jun , SANDHU, Gurtej
发明人： LIU, Jun , SANDHU, Gurtej
IPC分类号： G11C11/16 , G01R33/09 , G11B5/66 , H01F10/32
CPC分类号： G11C11/1675 , B82Y10/00 , B82Y25/00 , G01R33/093 , G01R33/1284 , G11C11/16 , H01F10/3218 , Y10S977/934
摘要： Spin current generators (100, 200, 300) and systems and methods for employing spin current generators (100, 200, 300). A spin current generator (100, 200, 300) may be configured to generate a spin current polarized in one direction (116, 120, 214, 310, 312), or a spin current selectively polarized in two directions (212). The spin current generator (100, 200, 300) may by employed in spintronics applications, wherein a spin current (116, 120, 212, 214, 310, 312) is desired.
摘要翻译：自旋电流发生器（100,200,300）以及采用自旋电流发生器（100,200,300）的系统和方法。自旋电流发生器（100,200,300）可以被配置为产生在一个方向（116,120,214,310,312）上偏振的自旋电流，或者在两个方向（212）上选择性地偏振的自旋电流。自旋电流发生器（100,200,300）可以用于自旋电子学应用中，其中期望自旋电流（116,120,212,214,310,312）。

8. 发明申请

WO2006026699A2 METHOD FOR INTEGRATED CIRCUIT FABRICATION USING PITCH MULTIPLICATION 审中-公开
标题翻译：使用PITCH MULTIPLICATION的集成电路制造方法
公开(公告)号：WO2006026699A2
公开(公告)日：2006-03-09
申请号：PCT/US2005/031094
申请日：2005-08-26
申请人： MICRON TECHNOLOGY, INC. , ABATCHEV, Mirzafer, K. , SANDHU, Gurtej , TRAN, Luan , RERICHA, William, T. , DURCAN, Mark, D.
发明人： ABATCHEV, Mirzafer, K. , SANDHU, Gurtej , TRAN, Luan , RERICHA, William, T. , DURCAN, Mark, D.
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/0338 , H01L21/3081 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139 , Y10S438/947 , Y10S438/95
摘要： Different sized features in the array 102 and in the periphery 104 of an integrated circuit 100 are patterned on a substrate 110 in a single step. In particular, a mixed pattern, combining two separately formed patterns 177, 230, is formed on a single mask layer 160 and then transferred to the underlying substrate 110. The first of the separately formed patterns, 177, is formed by pitch multiplication and the second of the separately formed patterns, 230, is formed by conventional photolithography. The first of the separately formed patterns, 177, includes features 175 that are below the resolution of the photolithographic process used to form the second of the separately formed patterns, 230. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers 175 having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers 175 to form the mask pattern 177. Thus, the spacers 175 form the mask 177 having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material 200 is deposited around the spacers 175. The spacers 175 are further protected using a hard mask 210 and then photoresist 220 is formed and patterned over the hard mask 210. The photoresist pattern 230 is transferred through the hard mask 210 to the protective material 200. The combination of the patterns 177 and 230 made out by the spacers 175 and the protective material 200 is then transferred to an underlying amorphous carbon hard mask layer 160. The combined pattern, having features of difference sizes, is then transferred to the underlying substrate 110.
摘要翻译：阵列102中和集成电路100的周边104中的不同尺寸的特征在单个步骤中在衬底110上图案化。特别地，组合两个单独形成的图案177,230的混合图案形成在单个掩模层160上，然后转移到下面的衬底110.单独形成的图案177中的第一个由间距倍增形成，并且通过常规光刻法形成分开形成的图案230的第二个。单独形成的图案177中的第一个包括低于用于形成第二个单独形成的图案230的光刻工艺的分辨率的特征175.这些线通过在光致抗蚀剂上形成图案然后蚀刻该图案成为无定形碳层。在无定形碳的侧壁上形成宽度小于无定形碳的未蚀刻部分的宽度的侧壁夹具175。然后去除无定形碳，留下侧壁间隔物175以形成掩模图案177.因此，间隔物175形成具有小于用于在光致抗蚀剂上形成图案的光刻工艺的分辨率的特征尺寸的掩模177。保护材料200沉积在间隔物175周围。使用硬掩模210进一步保护间隔物175，然后在硬掩模210上形成并图案化光致抗蚀剂220.光致抗蚀剂图案230通过硬掩模210转移到保护层然后将由间隔物175和保护材料200制成的图案177和230的组合转移到下面的无定形碳硬掩模层160.然后将具有不同尺寸特征的组合图案转移到底层衬底110。

9. 发明申请

WO2010135172A1 VERTICALLY-ORIENTED SELECTION TRANSISTOR STRUCTURE FOR CROSS-POINT MEMORY ARRAY 审中-公开
标题翻译：用于跨点记忆阵列的垂直选择晶体管结构
公开(公告)号：WO2010135172A1
公开(公告)日：2010-11-25
申请号：PCT/US2010/034840
申请日：2010-05-14
申请人： MICRON TECHNOLOGY, INC. , SANDHU, Gurtej , ZAHURAK, John, K. , PARKS, Jay
发明人： SANDHU, Gurtej , ZAHURAK, John, K. , PARKS, Jay
IPC分类号： H01L27/24
CPC分类号： H01L27/2454 , H01L27/2463 , H01L29/7827 , H01L45/06 , H01L45/1233
摘要： A vertical field-effect transistor structure is disclosed comprising a semiconductor material mesa (320) upstanding from a semiconductor base (555) that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first siliciure layers (352) on the surface of the base. The second doped region is electrically coupled to one of a plurality of second siliciure layers (351) on the upper surface of the mesa. A gate conductor (350) is provided on one or more sidewalls of the mesa. Resistive memory cells (220) may be coupled to the second siliciure layers to form a cross-point array.
摘要翻译：公开了垂直场效应晶体管结构，其包括从在第一和第二掺杂区域之间形成导电沟道的半导体基底（555）直立的半导体材料台面（320）。第一掺杂区域电耦合到基底表面上的一个或多个第一硅化物层（352）。第二掺杂区域电耦合到台面的上表面上的多个第二硅化物层（351）之一。栅极导体（350）设置在台面的一个或多个侧壁上。电阻式存储单元（220）可以耦合到第二硅化物层以形成交叉点阵列。

10. 发明申请

WO2009155067A2 METHOD FOR FORMING FINE PITCH STRUCTURES 审中-公开
标题翻译：形成细微结构的方法
公开(公告)号：WO2009155067A2
公开(公告)日：2009-12-23
申请号：PCT/US2009/045515
申请日：2009-05-28
申请人： MICRON TECHNOLOGY, INC. , SANDHU, Gurtej
发明人： SANDHU, Gurtej
IPC分类号： H01L21/027 , G03F7/20
CPC分类号： H01L21/76877 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/32139 , H01L21/76816 , H01L21/76838 , H01L27/105 , Y10T29/49146 , Y10T29/49155 , Y10T29/49165
摘要： A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g ., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels. The rows on different levels can crisscross one another. Selectively removing material from some of the rows can from openings to form, e.g ., contact vias.
摘要翻译：使用具有敞开内部空间的模具来限定图案。模具具有限定内部容积并抑制沉积的天花板，地板和侧壁。模具的一端是开放的，相对的端部具有用作种子侧壁的侧壁。第一种材料沉积在种子侧壁上。第二种材料沉积在沉积的第一种材料上。第一和第二材料的沉积是交替的，从而在内部容积中形成第一和第二材料的交替排。随后选择性地除去模具和种子层。此外，选择性地去除第一或第二材料中的一个，从而形成包括剩余材料的独立行的图案。独立行可以用作最终产品中的结构，例如集成电路，或者可以用作硬掩模结构以图案化下面的基底。模具和材料行可以在多个层次上形成。不同级别的行可以相互交叉。从一些行中选择性地去除材料可以从开口形成，例如接触通孔。

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