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1. 发明申请

WO2006130309A2 METHOD OF MANUFACTURING SIDEWALL SPACERS ON A MEMORY DEVICE, AND DEVICE COMPRISING SAME 审中-公开
标题翻译：在存储器件上制造隔板间隔的方法以及包含其的装置
公开(公告)号：WO2006130309A2
公开(公告)日：2006-12-07
申请号：PCT/US2006/017367
申请日：2006-05-05
申请人： MICRON TECHNOLOGY, INC. , HWANG, David, K. , PAREKH, Kunal , WILLETT, Michael , TRIVEDI, Jigish , MATHEW, Suraj , PETERSON, Greg
发明人： HWANG, David, K. , PAREKH, Kunal , WILLETT, Michael , TRIVEDI, Jigish , MATHEW, Suraj , PETERSON, Greg
IPC分类号： H01L27/105 , H01L21/8239 , H01L21/8247 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11543
摘要： The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness that is greater than the first thickness, the first and second sidewall spacers comprised of a material from a single layer of spacer material.
摘要翻译：本发明一般涉及在存储器件上制造侧壁间隔物的方法，以及包括这种侧壁间隔物的存储器件。在一个说明性实施例中，该方法包括在由存储器阵列和至少一个外围电路构成的存储器件上形成侧壁间隔物，该隔离物通过形成邻近存储器阵列中的字线结构的第一侧壁间隔物，第一侧壁间隔物具有第一厚度以及在所述外围电路中形成与所述晶体管结构相邻的第二侧壁间隔物，所述第二侧壁间隔物具有大于所述第一厚度的第二厚度，其中所述第一和第二侧壁间隔物包括来自单层间隔物材料的材料。在一个说明性实施例中，该装置包括由多个字线结构组成的存储器阵列，多个字线结构中的每一个具有与其相邻形成的第一侧壁间隔物，第一侧壁间隔物具有第一厚度，外围电路包括至少一个晶体管，其具有与其相邻形成的第二侧壁间隔物，所述第二侧壁间隔物具有大于第一厚度的第二厚度，所述第一和第二侧壁间隔物由来自单层间隔物材料的材料构成。

2. 发明申请

WO2006135505A2 CAPACITORLESS DRAM ON BULK SILICON 审中-公开
标题翻译：大容量无机硅电容器
公开(公告)号：WO2006135505A2
公开(公告)日：2006-12-21
申请号：PCT/US2006/017493
申请日：2006-05-05
申请人： MICRON TECHNOLOGY, INC. , MATHEW, Suraj , TRIVEDI, Jigish, D.
发明人： MATHEW, Suraj , TRIVEDI, Jigish, D.
IPC分类号： H01L21/84 , H01L27/12 , H01L29/78
CPC分类号： G11C7/00 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10882 , H01L27/1203 , H01L29/7841
摘要： A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate (10) is provided, and an array of silicon studs (16) is defined within the silicon substrate. An insulator layer (18) is defined atop at least a portion of the silicon substrate (10), and between the silicon studs (16). A silicon-over-insulator layer (22, 24) is defined surrounding the silicon studs (16) atop the insulator layer(18), and a capacitorless DRAM (26-40) is formed within and above the silicon-over-insulator layer (22, 24).
摘要翻译：在局部绝缘体上形成无电容器DRAM的方法包括以下步骤：提供硅衬底（10），并且硅衬底阵列（16）被限定在硅衬底内。绝缘体层（18）被限定在硅衬底（10）的至少一部分之上，并且在硅柱头（16）之间。绝缘体层（22,24）被限定为围绕绝缘体层（18）顶部的硅柱（16），并且在绝缘体上硅层内部和上方形成无电容器DRAM（26-40）（22,24）。

3. 发明申请

WO2007018967A2 METHODS OF FORMING MEMORY CIRCUITRY 审中-公开
标题翻译：形成存储器电路的方法
公开(公告)号：WO2007018967A2
公开(公告)日：2007-02-15
申请号：PCT/US2006/027366
申请日：2006-07-13
申请人： MICRON TECHNOLOGY, INC.
发明人： PAREKH, Kunal, R. , MATHEW, Suraj , COLE, Steve
IPC分类号： H01L21/336 , H01L21/8242 , H01L27/108
CPC分类号： H01L29/6656 , H01L27/10882 , H01L27/10891 , H01L27/10894
摘要： The invention includes methods of forming memory circuitry. In one implementation, a substrate is provided which has a memory array circuitry area and a peripheral circuitry area. The memory array circuitry area comprises transistor gate lines having a first minimum line spacing. The peripheral circuitry area comprises transistor gate lines having a second minimum line spacing which is greater than the first minimum line spacing. Anisotropically etched insulative sidewall spacers are formed over opposing sidewalls of individual of said transistor gate lines within the peripheral circuitry area prior to forming anisotropically etched insulative sidewall spacers over opposing sidewalls of individual of said transistor gate lines within the memory array area. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成存储器电路的方法。在一个实现中，提供了具有存储器阵列电路区域和外围电路区域的衬底。存储器阵列电路区域包括具有第一最小线间距的晶体管栅极线。外围电路区域包括具有大于第一最小线间距的第二最小线间距的晶体管栅极线。在存储器阵列区域内的所述晶体管栅极线的单独的相对侧壁上形成各向异性蚀刻的绝缘侧壁间隔物之前，在外围电路区域内的所述晶体管栅极线的单独的相对侧壁上形成各向异性蚀刻的绝缘侧壁间隔物。考虑了其他方面和实现。

4. 发明申请

WO2006104654A1 METHODS OF FORMING RECESSED ACCESS DEVICES 审中-公开
标题翻译：形成接入设备的方法
公开(公告)号：WO2006104654A1
公开(公告)日：2006-10-05
申请号：PCT/US2006/008295
申请日：2006-03-08
申请人： MICRON TECHNOLOGY, INC.
发明人： PAREKH, Kunal, R. , MATHEW, Suraj , TRIVEDI, Jigish, D. , ZAHURAK, John, K. , TANG, Sanh, D.
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10876 , H01L27/10823
摘要： The invention includes methods of forming recessed access devices (180, 182, 184, 186). A substrate (102) is provided to have recessed access device trenches therein. A pair of the recessed access device trenches (110) are adjacent one another. Electrically conductive material (144) is formed within the recessed access device trenches, and source/drain regions (170, 172, 174, 176, 178, 180) are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench (130) is formed between the adjacent recessed access devices and filled with electrically insulative material (136) to form a trenched isolation region.
摘要翻译：本发明包括形成凹入进入装置（180,182,184,186）的方法。衬底（102）设置成在其中具有凹进的存取装置沟槽。一对凹进的接入设备沟槽（110）彼此相邻。导电材料（144）形成在凹进的存取器件沟槽内，源/漏区（170,172,174,176,178,180）形成在导电材料附近。导电材料和源极/漏极区域一起被并入一对相邻的凹进入器件中。在凹陷的访问设备沟槽形成在衬底内之后，隔离区沟槽（130）形成在相邻的凹进的访问设备之间，并且填充有电绝缘材料（136）以形成沟槽的隔离区域。

5. 发明公开

EP1897135A2 CAPACITORLESS DRAM OVER LOCALIZED SOI 审中-公开
标题翻译：无缝式电容器DRAM对离体SOI
公开(公告)号：EP1897135A2
公开(公告)日：2008-03-12
申请号：EP06752344.9
申请日：2006-05-05
申请人： Micron Technology, Inc.
发明人： MATHEW, Suraj , TRIVEDI, Jigish, D.
IPC分类号： H01L21/84 , H01L27/12 , H01L29/78
CPC分类号： G11C7/00 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10882 , H01L27/1203 , H01L29/7841
摘要： A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate (10) is provided, and an array of silicon studs (16) is defined within the silicon substrate. An insulator layer (18) is defined atop at least a portion of the silicon substrate (10), and between the silicon studs (16). A silicon-over-insulator layer (22, 24) is defined surrounding the silicon studs (16) atop the insulator layer(18), and a capacitorless DRAM (26-40) is formed within and above the silicon-over-insulator layer (22, 24).

6. 发明公开

EP1911076A2 METHODS OF FORMING MEMORY CIRCUITRY WITH DIFFERENT INSULATIVE SIDEWALL SPACERS 审中-公开
标题翻译：方法存储器电路与不同的绝缘侧墙距表层形成
公开(公告)号：EP1911076A2
公开(公告)日：2008-04-16
申请号：EP06787295.2
申请日：2006-07-13
申请人： Micron Technology, Inc.
发明人： PAREKH, Kunal, R. , MATHEW, Suraj , COLE, Steve
IPC分类号： H01L21/336 , H01L21/8242 , H01L27/108
CPC分类号： H01L29/6656 , H01L27/10882 , H01L27/10891 , H01L27/10894
摘要： The invention includes methods of forming memory circuitry. In one implementation, a substrate (12) is provided which has a memory array circuitry area (14) and a peripheral circuitry area (16). The memory array circuitry area comprises transistor gate lines (15) having a first minimum line spacing (Dl). The peripheral circuitry area comprises transistor gate lines (17) having a second minimum line spacing (D2) which is greater than the first minimum line spacing. Anisotropically etched insulative sidewall spacer (34) are formed over opposing sidewalls of individual of said transistor gate lines within the peripheral circuitry area prior to forming anisotropically etched insulative sidewall spacers (40) over opposing sidewalls of individual of said transistor gate lines within the memory array area. Other aspects and implementations are contemplated.

7. 发明授权

EP1880421B1 METHODS OF FORMING RECESSED ACCESS DEVICES 有权
标题翻译：用于生产RECESSED接入设备
公开(公告)号：EP1880421B1
公开(公告)日：2014-07-16
申请号：EP06737463.7
申请日：2006-03-08
申请人： Micron Technology, Inc.
发明人： PAREKH, Kunal, R. , MATHEW, Suraj , TRIVEDI, Jigish, D. , ZAHURAK, John, K. , TANG, Sanh, D.
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10876 , H01L27/10823

8. 发明公开

EP1880421A1 METHODS OF FORMING RECESSED ACCESS DEVICES 有权
标题翻译：用于生产RECESSED接入设备
公开(公告)号：EP1880421A1
公开(公告)日：2008-01-23
申请号：EP06737463.7
申请日：2006-03-08
申请人： Micron Technology, Inc.
发明人： PAREKH, Kunal, R. , MATHEW, Suraj , TRIVEDI, Jigish, D. , ZAHURAK, John, K. , TANG, Sanh, D.
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10876 , H01L27/10823
摘要： The invention includes methods of forming recessed access devices (180, 182, 184, 186). A substrate (102) is provided to have recessed access device trenches therein. A pair of the recessed access device trenches (110) are adjacent one another. Electrically conductive material (144) is formed within the recessed access device trenches, and source/drain regions (170, 172, 174, 176, 178, 180) are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench (130) is formed between the adjacent recessed access devices and filled with electrically insulative material (136) to form a trenched isolation region.

9. 发明授权

EP1883965B1 MEMORY DEVICE HAVING SIDEWALL SPACERS AND METHOD OF FORMING THEREOF 有权
标题翻译：与侧壁间隔及其制造方法存储器元件
公开(公告)号：EP1883965B1
公开(公告)日：2016-10-05
申请号：EP06784391.2
申请日：2006-05-05
申请人： Micron Technology, Inc.
发明人： HWANG, David, K. , PAREKH, Kunal , WILLETT, Michael , TRIVEDI, Jigish , MATHEW, Suraj , PETERSON, Greg
IPC分类号： H01L27/115 , H01L27/108 , H01L27/105 , H01L21/8239 , H01L21/8242 , H01L21/8247
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11543

10. 发明公开

EP1883965A2 METHOD OF MANUFACTURING SIDEWALL SPACERS ON A MEMORY DEVICE, AND DEVICE COMPRISING SAME 有权
标题翻译：与侧壁间隔及其制造方法存储器元件
公开(公告)号：EP1883965A2
公开(公告)日：2008-02-06
申请号：EP06784391.2
申请日：2006-05-05
申请人： Micron Technology, Inc.
发明人： HWANG, David, K. , PAREKH, Kunal , WILLETT, Michael , TRIVEDI, Jigish , MATHEW, Suraj , PETERSON, Greg
IPC分类号： H01L27/105 , H01L21/8239 , H01L21/8247 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11543
摘要： The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness that is greater than the first thickness, the first and second sidewall spacers comprised of a material from a single layer of spacer material.

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