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1. 发明申请

WO2022133705A1 LOW POWER MANAGEMENT FOR SLEEP MODE OPERATION OF A MEMORY DEVICE 审中-公开
公开(公告)号：WO2022133705A1
公开(公告)日：2022-06-30
申请号：PCT/CN2020/138229
申请日：2020-12-22
申请人： MICRON TECHNOLOGY, INC.
发明人： XU, Shuai , PICCARDI, Michele , MURALIDHARAN, Arvind , LEE, June , LIN, Qisong , STOLLER, Scott A. , SHEN, Jun
IPC分类号： G11C5/00
摘要： A determination is made that a memory device of a memory sub-system is to be transitioned to a sleep mode. A command is initiated to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state. In the low power mode, a reference voltage is supplied to a voltage regulator of the standby circuit to supply a standby current level to the memory device during the sleep mode.

2. 发明申请

WO2009015312A1 PROGRAMMING MULTILEVEL CELL MEMORY ARRAYS 审中-公开
标题翻译：编程多个单元格存储器阵列
公开(公告)号：WO2009015312A1
公开(公告)日：2009-01-29
申请号：PCT/US2008/071117
申请日：2008-07-25
申请人： MICRON TECHNOLOGY, INC. , LEE, June
发明人： LEE, June
IPC分类号： G11C16/04 , G11C16/00 , G11B20/10
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C2211/5621
摘要： Methods and apparatus, such as those for programming of multilevel cell NAND memory arrays to facilitate a reduction of program disturb, are disclosed. In one such method, memory cells are shifted from a first Vt distribution to a second Vt distribution higher than the first Vt distribution during a first portion of a programming operation if a second or a fourth data state is desired, while memory cells remain in the first Vt distribution if the first or a third data state is desired. During a second portion of the programming operating, if the third data state is desired, those memory cells are shifted from the first Vt distribution to a third Vt distribution higher than the second Vt distribution and, if the fourth data state is desired, those memory cells are shifted from the second Vt distribution to a fourth Vt distribution higher than the third Vt distribution.
摘要翻译：公开了诸如用于编程多电平单元NAND存储器阵列以便于减少程序干扰的方法和装置。在一种这样的方法中，如果需要第二或第四数据状态，则在编程操作的第一部分期间，存储器单元从第一Vt分布移位到高于第一Vt分布的第二Vt分布，而存储单元保留在如果需要第一或第三数据状态，则首先进行Vt分配。在编程操作的第二部分期间，如果需要第三数据状态，那些存储单元从第一Vt分布移位到高于第二Vt分布的第三Vt分布，并且如果需要第四数据状态，那些存储器单元从第二Vt分布移位到高于第三Vt分布的第四Vt分布。

3. 发明申请

WO2009058434A2 SYSTEMS, METHODS AND DEVICES FOR LIMITING CURRENT CONSUMPTION UPON POWER-UP 审中-公开
标题翻译：用于限制上电消耗电流的系统，方法和设备
公开(公告)号：WO2009058434A2
公开(公告)日：2009-05-07
申请号：PCT/US2008/068856
申请日：2008-06-30
申请人： MICRON TECHNOLOGY, INC. , LEE, June
发明人： LEE, June
CPC分类号： G06F1/266 , G06F1/3296 , G11C5/143 , G11C5/147 , G11C16/30
摘要： Embodiments are described including those for controlling peak current consumption of a multi-chip memory package during power-up. In one embodiment, each memory device of the multi-chip package includes a power level detector used to compare an internal voltage signal to a threshold. A current limiter controls the ramping rate of the internal voltage signal in response to the power level detector as the internal voltage signal ramps up towards the threshold.
摘要翻译：描述了实施例，其包括用于在上电期间控制多芯片存储器封装的峰值电流消耗的实施例。在一个实施例中，多芯片封装的每个存储器件包括用于将内部电压信号与阈值进行比较的功率电平检测器。当内部电压信号上升到阈值时，电流限制器响应于功率电平检测器来控制内部电压信号的斜坡率。

4. 发明申请

WO2008134396A1 PROGRAMMING AND/OR ERASING A MEMORY DEVICE IN RESPONSE TO ITS PROGRAM AND/OR ERASE HISTORY 审中-公开
标题翻译：对其程序和/或删除历史进行编程和/或删除存储器件
公开(公告)号：WO2008134396A1
公开(公告)日：2008-11-06
申请号：PCT/US2008/061376
申请日：2008-04-24
申请人： MICRON TECHNOLOGY, INC. , LEE, June , JAFFIN, Fred
发明人： LEE, June , JAFFIN, Fred
IPC分类号： G11C16/10 , G11C16/34
CPC分类号： G11C16/12 , G06F11/1068 , G06F2212/202 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/20 , G11C16/26 , G11C16/349
摘要： For one embodiment, a program starting voltage of one or more program pulses applied to one or more memory cells (308) is in response, at least in part, to a number of program pulses previously required to program the one or more memory cells and/or an erase starting voltage of one or more erase pulses applied to one or more memory cells (308) is based on a number of erase pulses previously required to erase the one or more memory cells (308). For another embodiment, the adjustment of a program starting voltage level and/or an erase starting voltage level of one or more program and/or erase pulses applied to one or more memory cells (308) is in response, at least in part, to a number of program/erase cycles previously applied to the one or more memory cells (308).
摘要翻译：对于一个实施例，施加到一个或多个存储器单元（308）的一个或多个编程脉冲的程序启动电压至少部分地响应于先前需要编程一个或多个存储器单元的编程脉冲数，以及施加到一个或多个存储单元（308）的一个或多个擦除脉冲的擦除起始电压基于先前需要擦除一个或多个存储器单元（308）的擦除脉冲数。对于另一实施例，施加到一个或多个存储器单元（308）的一个或多个编程和/或擦除脉冲的程序启动电压电平和/或擦除开始电压电平的调整至少部分地响应于先前施加到一个或多个存储器单元（308）的多个编程/擦除循环。

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