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1. 发明申请

WO2019118125A1 MULTILEVEL ADDRESSING 审中-公开
公开(公告)号：WO2019118125A1
公开(公告)日：2019-06-20
申请号：PCT/US2018/061201
申请日：2018-11-15
申请人： MICRON TECHNOLOGY, INC.
发明人： FERRANTE, Gianfranco , MINOPOLI, Dionisio
IPC分类号： G06F12/02
摘要： In an example, a starting address corresponding to a location of particular information within a non-volatile storage memory is determined during an initialization process using a multilevel addressing scheme. Using the multilevel addressing scheme may include performing multiple reads of the storage memory at respective address levels to determine the starting address corresponding to the location of the particular information.

2. 发明申请

WO2021069943A1 SELF-ADAPTIVE WEAR LEVELING METHOD AND ALGORITHM 审中-公开
公开(公告)号：WO2021069943A1
公开(公告)日：2021-04-15
申请号：PCT/IB2019/000970
申请日：2019-10-09
申请人： MICRON TECHNOLOGY, INC.
发明人： FERRANTE, Gianfranco , BALLUCHI, Daniele , MINOPOLI, Dionisio
IPC分类号： G06F12/02
摘要： The present disclosure relates to a method for data relocation in memory having two portions of data. An embodiment includes a memory having a plurality of physical blocks of memory cells, and a first and second portion of data having a first and second, respectively, number of logical block addresses associated therewith. Two of the plurality of physical blocks of cells do not have data stored therein. In the method, the data of the first portion that is associated with one of the first number of logical block addresses is relocated to one of the two physical blocks of cells that don't have data stored therein, and the data of the second portion that is associated with one of the second number of logical block addresses is relocated to the other one of the two physical blocks of cells that don't have data stored therein.

3. 发明申请

WO2019182717A1 INTERFACE FOR MEMORY HAVING A CACHE AND MULTIPLE INDEPENDENT ARRAYS 审中-公开
公开(公告)号：WO2019182717A1
公开(公告)日：2019-09-26
申请号：PCT/US2019/019066
申请日：2019-02-22
申请人： MICRON TECHNOLOGY, INC.
发明人： MINOPOLI, Dionisio , FERRANTE, Gianfranco , CAPRI, Antonino , CONFALONIERI, Emanuele , BALLUCHI, Daniele
IPC分类号： G06F3/06
摘要： The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.

4. 发明申请

WO2017053411A1 SYSTEMS AND METHODS FOR PROVIDING FILE INFORMATION IN A MEMORY SYSTEM PROTOCOL 审中-公开
标题翻译：用于在存储器系统协议中提供文件信息的系统和方法
公开(公告)号：WO2017053411A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/052864
申请日：2016-09-21
申请人： MICRON TECHNOLOGY, INC.
发明人： CARACCIO, Danilo , MIRICHIGNI, Graziano , SANTOPIETRO, Gianfranco , FERRANTE, Gianfranco , CONFALONIERI, Emanuele
IPC分类号： G06F13/42
CPC分类号： G06F3/0643 , G06F3/061 , G06F3/0679
摘要： A memory device (14) includes a memory component (26) and controller circuitry (23). The memory component (26) stores data and the controller circuitry (23) receives, from a host electronic device (12), one or more commands of a memory system protocol (16). The one or more commands include at least one write command, the write command comprising one or more blocks of data to be stored in the memory component (26). Further, the one or more commands include metadata, attributes (28), or both related to the one or more blocks of data. The controller circuitry (23) interprets and executes the one or more commands. Accordingly, the blocks are stored in the memory component (26). Further, the controller circuitry (23) of the memory device (14) has access to the metadata, attributes (28) or both.
摘要翻译：存储器件（14）包括存储器组件（26）和控制器电路（23）。存储器组件（26）存储数据，并且控制器电路（23）从主机电子设备（12）接收存储器系统协议（16）的一个或多个命令。一个或多个命令包括至少一个写入命令，该写入命令包括要存储在存储器组件（26）中的一个或多个数据块。此外，一个或多个命令包括与一个或多个数据块相关的元数据，属性（28）或二者。控制器电路（23）解释并执行一个或多个命令。因此，这些块被存储在存储器组件26中。此外，存储器设备（14）的控制器电路（23）可以访问元数据，属性（28）或两者。

5. 发明公开

EP3724769A1 MULTILEVEL ADDRESSING 无效
公开(公告)号：EP3724769A1
公开(公告)日：2020-10-21
申请号：EP18888075.1
申请日：2018-11-15
申请人： Micron Technology, Inc.
发明人： FERRANTE, Gianfranco , MINOPOLI, Dionisio
IPC分类号： G06F12/02

6. 发明公开

EP3769204A1 INTERFACE FOR MEMORY HAVING A CACHE AND MULTIPLE INDEPENDENT ARRAYS 无效
公开(公告)号：EP3769204A1
公开(公告)日：2021-01-27
申请号：EP19772321.6
申请日：2019-02-22
申请人： Micron Technology, Inc.
发明人： MINOPOLI, Dionisio , FERRANTE, Gianfranco , CAPRI, Antonino , CONFALONIERI, Emanuele , BALLUCHI, Daniele
IPC分类号： G06F3/06

7. 发明公开

EP4042283A1 SELF-ADAPTIVE WEAR LEVELING METHOD AND ALGORITHM 无效
公开(公告)号：EP4042283A1
公开(公告)日：2022-08-17
申请号：EP19948398.3
申请日：2019-10-09
申请人： MICRON TECHNOLOGY, INC.
发明人： FERRANTE, Gianfranco , BALLUCHI, Daniele , MINOPOLI, Dionisio
IPC分类号： G06F12/02

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