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1. 发明申请

WO2010102235A1 FAULT DIAGNOSIS FOR NON-VOLATILE MEMORIES 审中-公开
标题翻译：故障诊断非易失性存储器
公开(公告)号：WO2010102235A1
公开(公告)日：2010-09-10
申请号：PCT/US2010/026403
申请日：2010-03-05
申请人： MENTOR GRAPHICS CORPORATION , MUKHERJEE, Nilanjan , POGIEL, Artur , RAJSKI, Janusz , TYSZER, Jerzy
发明人： MUKHERJEE, Nilanjan , POGIEL, Artur , RAJSKI, Janusz , TYSZER, Jerzy
IPC分类号： G11C29/20 , G11C29/40 , G11C29/56
CPC分类号： G11C29/40 , G11C16/04 , G11C17/14 , G11C29/20 , G11C29/56 , G11C29/56008 , G11C2029/0401 , G11C2029/1208 , G11C2029/5606
摘要： Fault diagnosis techniques for non-volatile memories are disclosed. The techniques are based on deterministic partitioning of rows and/or columns of cells in a memory array. Through deterministic partitioning, signatures are generated for identification of failing rows, columns and single memory cells. A row/column selector or a combined row and column selector may be built on chip to implement the process of deterministic partitioning. An optional shadow register may be used to transfer obtained signatures to an automated test equipment (ATE).
摘要翻译：公开了用于非易失性存储器的故障诊断技术。这些技术基于对存储器阵列中的单元格行和/或列的确定性划分。通过确定性分区，生成签名以识别失败的行，列和单个存储单元。行/列选择器或组合的行和列选择器可以构建在芯片上以实现确定性分区的过程。可以使用可选的影子寄存器将获得的签名转移到自动测试设备（ATE）。

2. 发明申请

WO2009039316A2 FAULT DIAGNOSIS IN A MEMORY BIST ENVIRONMENT 审中-公开
标题翻译：记忆环境中的故障诊断
公开(公告)号：WO2009039316A2
公开(公告)日：2009-03-26
申请号：PCT/US2008/076911
申请日：2008-09-18
申请人： MENTOR GRAPHICS CORPORATION , MUKHERJEE, Nilanjan , POGIEL, Artur , RAJSKI, Janusz , TYSZER, Jerzy
发明人： MUKHERJEE, Nilanjan , POGIEL, Artur , RAJSKI, Janusz , TYSZER, Jerzy
IPC分类号： G06F11/25
CPC分类号： G11C29/56 , G11C29/40 , G11C29/44 , G11C29/56008 , G11C2029/1208
摘要： Disclosed are methods and devices for temporally compacting test response signatures of failed memory tests in a memory built-in self-test environment, to provide the ability to carry on memory built-in self-test operations even with the detection of multiple time related memory test failures. In some implementations of the invention, the compacted test response signatures are provided to an automated test equipment device along with memory location information. According to various implementations of the invention, an integrated circuit with embedded memory and a memory BIST controller also includes a linear feedback structure for use as a signature register that can temporally compact test response signatures from the embedded memory array during a test step of a memory test. In various implementations the integrated circuit may also include a failing words counter, a failing column indicator, and/or a failing row indicator to collect memory location information for a failing test response.
摘要翻译：公开的是用于在存储器内置自检环境中暂时压缩失败存储器测试的测试响应签名的方法和设备，以提供即使在检测多个时间相关存储器的情况下进行存储器内置自检操作的能力测试失败。在本发明的一些实施方案中，将压实的测试响应签名与存储器位置信息一起提供给自动测试设备设备。根据本发明的各种实现方式，具有嵌入式存储器和存储器BIST控制器的集成电路还包括用作签名寄存器的线性反馈结构，其可以在存储器的测试步骤期间临时压缩来自嵌入式存储器阵列的测试响应签名测试。在各种实现中，集成电路还可以包括故障字计数器，故障列指示符和/或故障行指示符以收集故障测试响应的存储器位置信息。

3. 发明申请

WO2004072660A2 COMPRESSING TEST RESPONSES USING A COMPACTOR 审中-公开
标题翻译：使用压缩机压缩测试响应
公开(公告)号：WO2004072660A2
公开(公告)日：2004-08-26
申请号：PCT/US2004/004271
申请日：2004-02-13
申请人： MENTOR GRAPHICS CORPORATION , RAJSKI, Janusz , TYSZER, Jerzy , WANG, Chen , MRUGALSKI, Grzegorz , POGIEL, Artur
发明人： RAJSKI, Janusz , TYSZER, Jerzy , WANG, Chen , MRUGALSKI, Grzegorz , POGIEL, Artur
IPC分类号： G01R
CPC分类号： G01R31/318566 , G01R31/31703 , G01R31/318536 , G01R31/318583 , G01R31/31921 , G11C29/40 , G11C29/48 , G11C2029/3202
摘要： The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation ("EDA") software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.
摘要翻译：本公开描述了用于压缩集成电路中的测试结果的压实机的实施例以及用于使用和设计这些实施例的方法。所公开的压实机可以用作例如任何基于扫描的设计的一部分。此外，任何公开的压实机可以在诸如电子设计自动化（“EDA”）软件工具的计算机执行的应用中被设计，模拟和/或验证。还描述了在公开的压实机实施例中用于诊断故障的方法的实施例。

4. 发明公开

EP2201575A2 FAULT DIAGNOSIS IN A MEMORY BIST ENVIRONMENT USING A LINEAR FEEDBACK SHIFT REGISTER 审中-公开
标题翻译：麻烦存储器BIST环境中使用线性反馈移位寄存器
公开(公告)号：EP2201575A2
公开(公告)日：2010-06-30
申请号：EP08831305.1
申请日：2008-09-18
申请人： MENTOR GRAPHICS CORPORATION
发明人： MUKHERJEE, Nilanjan , POGIEL, Artur , RAJSKI, Janusz , TYSZER, Jerzy
IPC分类号： G11C29/56 , G11C29/40
CPC分类号： G11C29/56 , G11C29/40 , G11C29/44 , G11C29/56008 , G11C2029/1208
摘要： Disclosed are methods and devices for temporally compacting test response signatures of failed memory tests in a memory built-in self -test environment, to provide the ability to carry on memory built-in self-test operations even with the detection of multiple time related memory test failures. In some implementations of the invention, the compacted test response signatures are provided to an automated test equipment device along with memory location information. According to various implementations of the invention, an integrated circuit with embedded memory (204) and a memory BIST controller (206) also includes a linear feedback structure (410) for use as a signature register that can temporally compact test response signatures from the embedded memory array during a test step of a memory test. In various implementations the integrated circuit may also include a failing words counter (211), a failing column indicator (213), and/or a failing row indicator (214) to collect memory location information for a failing test response.

5. 发明公开

EP1595211A2 COMPRESSING TEST RESPONSES USING A COMPACTOR 有权转让
标题翻译： COMPRESS考试答案使用压路机
公开(公告)号：EP1595211A2
公开(公告)日：2005-11-16
申请号：EP04700016.1
申请日：2004-02-13
申请人： Mentor Graphics Corporation
发明人： RAJSKI, Janusz , TYSZER, Jerzy , WANG, Chen , MRUGALSKI, Grzegorz , POGIEL, Artur
IPC分类号： G06F11/00
CPC分类号： G01R31/318566 , G01R31/31703 , G01R31/318536 , G01R31/318583 , G01R31/31921 , G11C29/40 , G11C29/48 , G11C2029/3202
摘要： The present disclosure describes embodiments of a compactor (706) for compressing test results in an integrated circuit (704) and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation ('EDA') software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.

6. 发明授权

EP1595211B1 COMPRESSING TEST RESPONSES USING A COMPACTOR 有权转让
标题翻译： COMPRESS考试答案使用压路机
公开(公告)号：EP1595211B1
公开(公告)日：2008-07-09
申请号：EP04700016.1
申请日：2004-02-13
申请人： Mentor Graphics Corporation
发明人： RAJSKI, Janusz , TYSZER, Jerzy , WANG, Chen , MRUGALSKI, Grzegorz , POGIEL, Artur
IPC分类号： G06F11/00 , G01R31/3185
CPC分类号： G01R31/318566 , G01R31/31703 , G01R31/318536 , G01R31/318583 , G01R31/31921 , G11C29/40 , G11C29/48 , G11C2029/3202
摘要： The present disclosure describes embodiments of a compactor (706) for compressing test results in an integrated circuit (704) and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation ('EDA') software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.

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