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1. 发明申请

US20080011423A1 DEVICE AND METHOD FOR ETCHING FLASH MEMORY GATE STACKS COMPRISING HIGH-K DIELECTRIC 审中-公开
标题翻译：用于蚀刻包含高K电介质的闪存存储器栅极堆叠的装置和方法
公开(公告)号：US20080011423A1
公开(公告)日：2008-01-17
申请号：US11777714
申请日：2007-07-13
申请人： MEIHUA SHEN , Xikun Wang , Wei Liu , Yan Du , Shashank Deshmukh
发明人： MEIHUA SHEN , Xikun Wang , Wei Liu , Yan Du , Shashank Deshmukh
IPC分类号： C23F1/00
CPC分类号： H01L21/32136 , H01L21/31116
摘要： In one implementation, a method for etching a flash memory high-k gate stack on a workpiece is provided which includes etching a conductive material layer in a low temperature plasma chamber and etching a high-k dielectric layer in a high temperature plasma chamber. The workpiece is transferred between the low temperature plasma chamber and the high temperature plasma chamber through a vacuum transfer chamber connecting the low temperature plasma chamber and the high temperature plasma chamber. In one embodiment, an integrated etch station for etching a high-k flash memory structure is provided, which includes an etch chamber configured for plasma etch processing of a conductive material layer connected via a transfer chamber to an etch chamber configured for plasma etch processing of a high-k dielectric layer.
摘要翻译：在一个实施方案中，提供了一种用于蚀刻工件上的闪存高k栅极堆叠的方法，其包括在低温等离子体室中蚀刻导电材料层并蚀刻高温等离子体室中的高k电介质层。工件通过连接低温等离子体室和高温等离子体室的真空传送室在低温等离子体室和高温等离子体室之间传递。在一个实施例中，提供了用于蚀刻高k闪速存储器结构的集成蚀刻站，其包括蚀刻室，其被配置用于经由传送室连接到导电材料层的等离子体蚀刻处理到蚀刻室，所述蚀刻室被配置用于等离子体蚀刻处理高k电介质层。

2. 发明申请

US20080146034A1 METHOD FOR RECESS ETCHING 审中-公开
标题翻译：记忆蚀刻方法
公开(公告)号：US20080146034A1
公开(公告)日：2008-06-19
申请号：US11954981
申请日：2007-12-12
申请人： MEIHUA SHEN , RONG CHEN , Scott M. Williams
发明人： MEIHUA SHEN , RONG CHEN , Scott M. Williams
IPC分类号： H01L21/311
CPC分类号： H01L21/3065 , H01L21/30655 , H01L29/66636 , H01L29/7848
摘要： Methods for recess etching are provided herein that advantageously improve lateral to vertical etch ratio requirements, thereby enabling deeper recess etching while maintaining relatively shallow vertical etch depths. Such enhanced lateral etch methods advantageously provide benefits for numerous applications where lateral to vertical etch depth ratios are constrained or where recesses or cavities are desired to be formed. In some embodiments, a method of recess etching includes providing a substrate having a structure formed thereon; forming a recess in the substrate at least partially beneath the structure using a first etch process; forming a selective passivation layer on the substrate; and extending the recess in the substrate using a second etch process. The selective passivation layer is generally formed on regions of the substrate adjacent to the structure but generally not within the recess. The first and second etch processes may be the same or different.
摘要翻译：本文提供凹槽蚀刻的方法，其有利地提高了横向垂直蚀刻比要求，从而实现更深的凹槽蚀刻，同时保持较浅的垂直蚀刻深度。这种增强的横向蚀刻方法有利地为许多应用提供了优点，其中横向到垂直蚀刻深度比被约束或者需要形成凹部或空腔。在一些实施例中，凹陷蚀刻的方法包括提供其上形成有结构的基板; 使用第一蚀刻工艺在所述结构的至少部分下方在所述衬底中形成凹部; 在衬底上形成选择性钝化层; 以及使用第二蚀刻工艺在所述衬底中延伸所述凹部。选择性钝化层通常形成在与结构相邻的基底的区域上，但通常不在凹部内。第一和第二蚀刻工艺可以相同或不同。

3. 发明申请

US20120088371A1 METHODS FOR ETCHING SUBSTRATES USING PULSED DC VOLTAGE 审中-公开
标题翻译：使用脉冲直流电压蚀刻基板的方法
公开(公告)号：US20120088371A1
公开(公告)日：2012-04-12
申请号：US13089374
申请日：2011-04-19
申请人： ALOK RANJAN , NICOLAS GANI , MEIHUA SHEN , ANISUL H. KHAN
发明人： ALOK RANJAN , NICOLAS GANI , MEIHUA SHEN , ANISUL H. KHAN
IPC分类号： H01L21/3065
CPC分类号： H01L21/3065 , H01J37/32082 , H01J37/32697 , H01J2237/334 , H01L21/31116 , H01L21/32136
摘要： Methods for etching substrates using a pulsed DC voltage are provided herein. In some embodiments, a method for method for etching a substrate disposed on a substrate support within a process chamber may include providing a process gas to the process chamber; forming a plasma from the process gas; applying a pulsed DC voltage to a first electrode disposed within the process chamber; and etching the substrate while applying the pulsed DC voltage.
摘要翻译：本文提供了使用脉冲DC电压蚀刻基板的方法。在一些实施例中，用于蚀刻设置在处理室内的衬底支撑件上的衬底的方法的方法可包括向处理室提供工艺气体; 从工艺气体形成等离子体; 向设置在处理室内的第一电极施加脉冲DC电压; 并在施加脉冲DC电压的同时刻蚀衬底。

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