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1. 发明申请

WO2006065523A2 APPARATUS AND METHOD FOR MEMORY OPERATIONS USING ADDRESS-DEPENDENT CONDITIONS 审中-公开
标题翻译：使用地址相关条件的存储器操作的装置和方法
公开(公告)号：WO2006065523A2
公开(公告)日：2006-06-22
申请号：PCT/US2005/043074
申请日：2005-11-29
申请人： MATRIX SEMICONDUCTOR, INC. , SO, Kenneth, K. , FASOLI, Luca, G. , SCHEUERLEIN, Roy, E.
发明人： SO, Kenneth, K. , FASOLI, Luca, G. , SCHEUERLEIN, Roy, E.
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C11/1677
摘要： An apparatus is disclosed comprising a plurality of word lines and word line drivers, a plurality of bit lines and bit line drivers, and a plurality of memory cells coupled between respective word lines and bit lines. The apparatus also comprises circuitry operative to select a writing and/or reading condition to apply to a memory cell based on the memory cell’s location with respect to one or both of a word line driver and a bit line driver. The apparatus can also comprise circuitry that is operative to select a number of memory cells to be programmed in parallel based on memory cell location with respect to a word line and/or bit line driver.
摘要翻译：公开了一种包括多个字线和字线驱动器，多个位线和位线驱动器以及耦合在各个字线和位线之间的多个存储器单元的装置。该装置还包括电路，用于基于相对于字线驱动器和位线驱动器中的一个或两者的存储单元的位置来选择写入和/或读取条件以应用于存储器单元。该装置还可以包括电路，其可操作以基于相对于字线和/或位线驱动器的存储器单元位置来并行地选择要编程的多个存储器单元。

2. 发明申请

WO2004090905A2 THREE-DIMENSIONAL MEMORY DEVICE INCORPORATING SEGMENTED BIT LINE MEMORY ARRAY 审中-公开
标题翻译：配有SEGMENTED位线记忆阵列的三维存储器件
公开(公告)号：WO2004090905A2
公开(公告)日：2004-10-21
申请号：PCT/US2004/009756
申请日：2004-03-31
申请人： MATRIX SEMICONDUCTOR, INC. , SCHEUERLEIN, Roy, E. , ILKBAHAR, Alper , FASOLI, Luca, G.
发明人： SCHEUERLEIN, Roy, E. , ILKBAHAR, Alper , FASOLI, Luca, G.
IPC分类号： G11C7/18
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/0466 , G11C17/12 , G11C17/18 , G11C2213/71 , G11C2213/77 , Y10S257/91
摘要： A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line.
摘要翻译：三维（3D）高密度存储器阵列包括多个分段位线（即感测线），其中存储器阵列内的段切换器件将段连接到全局位线。分段交换设备驻留在集成电路的一个或多个层上，优选地驻留在每个位线层上。全局位线优选地位于存储器阵列下方的一个层上，但可驻留在多于一个层上。位线段优选地共享到相关联的全局位线的垂直连接。

3. 发明申请

WO2006073735A1 APPARATUS AND METHOD FOR HIERARCHICAL DECODING OF DENSE MEMORY ARRAYS USING MULTIPLE LEVELS OF MULTIPLE-HEADED DECODERS 审中-公开
标题翻译：使用多级解码器的多级别进行DENSE存储器阵列的分层解码的装置和方法
公开(公告)号：WO2006073735A1
公开(公告)日：2006-07-13
申请号：PCT/US2005/045564
申请日：2005-12-16
申请人： MATRIX SEMICONDUCTOR, INC. , FASOLI, Luca, G. , SO, Kenneth, K.
发明人： FASOLI, Luca, G. , SO, Kenneth, K.
IPC分类号： G11C5/06
CPC分类号： G11C8/10 , G11C16/08 , Y10T29/49002
摘要： A memory array comprising array lines of first and second types coupled to memory cells includes a first hierarchical decoder circuit for decoding address information and selecting one or more array lines of the first type. The first hierarchical decoder circuit includes at least two hierarchical levels of multi-headed decoder circuits. The first hierarchical decoder circuit may include a first-level decoder circuit for decoding a plurality of address signal inputs and generating a plurality of first-level decoded outputs, a plurality of second-level multi-headed decoder circuits, each respective one coupled to a respective first-level decoded output, each for providing a respective plurality of second-level decoded outputs, and a plurality of third-level multi-headed decoder circuits, each respective one coupled to a respective second-level decoded output, each for providing a respective plurality of third-level decoded outputs coupled to the memory array.
摘要翻译：包括耦合到存储器单元的第一和第二类型的阵列线的存储器阵列包括用于解码地址信息并选择第一类型的一个或多个阵列线的第一分层解码器电路。第一分层解码器电路包括至少两个分层级的多头解码器电路。第一分层解码器电路可以包括用于对多个地址信号输入进行解码并生成多个第一级解码输出的第一级解码器电路，多个第二级多头解码器电路，每个相应的一个耦合到各自的第一级解码输出，每个用于提供相应的多个第二级解码输出，以及多个第三级多头解码器电路，每个解码器电路分别耦合到相应的二级解码输出，每个用于提供一个耦合到存储器阵列的相应的多个第三级解码输出。

4. 发明申请

WO2009158676A1 CAPACITIVE DISCHARGE METHOD FOR WRITING TO NON-VOLATILE MEMORY 审中-公开
标题翻译：用于写入非易失性存储器的电容式放电方法
公开(公告)号：WO2009158676A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048955
申请日：2009-06-26
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , FASOLI, Luca, G. , YAN, Tianhong
发明人： SCHEUERLEIN, Roy, E. , FASOLI, Luca, G. , YAN, Tianhong
IPC分类号： G11C13/00 , G11C7/22
CPC分类号： G11C13/0007 , G11C7/12 , G11C7/22 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/71
摘要： A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The circuits for limiting the SET current provide a charge on one or more bit lines that is not sufficient to SET the memory cells, and then discharge the bit lines through the memory cells in order to SET the memory cells.
摘要翻译：存储器系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储器单元的三维存储器阵列（衬底上方），以及用于限制用于可逆电阻切换的SET电流的电路元素。用于限制SET电流的电路在不足以设置存储器单元的一个或多个位线上提供电荷，然后通过存储器单元放电位线以设置存储器单元。

5. 发明申请

WO2008016950A2 METHOD AND APPARATUS FOR MEMORY ARRAY INCORPORATING TWO DATA BUSSES FOR MEMORY ARRAY BLOCK SELECTION 审中-公开
标题翻译：用于存储阵列选择的两个数据总线的存储器阵列的方法和装置
公开(公告)号：WO2008016950A2
公开(公告)日：2008-02-07
申请号：PCT/US2007/074903
申请日：2007-07-31
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , FASOLI, Luca, G. , PETTI, Christopher, J.
发明人： SCHEUERLEIN, Roy, E. , FASOLI, Luca, G. , PETTI, Christopher, J.
IPC分类号： G11C16/04
CPC分类号： G11C17/18 , G11C5/063 , G11C8/08 , G11C8/10 , G11C8/12 , G11C8/14
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

6. 发明申请

WO2008016948A2 METHOD AND APPARATUS FOR DUAL DATA-DEPENDENT BUSSES FOR COUPLING READ/WRITE CIRCUITS TO A MEMORY ARRAY 审中-公开
标题翻译：用于将读/写电路耦合到存储阵列的双数据相关总线的方法和装置
公开(公告)号：WO2008016948A2
公开(公告)日：2008-02-07
申请号：PCT/US2007/074901
申请日：2007-07-31
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , FASOLI, Luca, G.
发明人： SCHEUERLEIN, Roy, E. , FASOLI, Luca, G.
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C8/12 , G11C7/1048 , G11C7/18 , G11C8/08
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

7. 发明申请

WO2006121529A2 METHOD AND APPARATUS FOR INCORPORATING BLOCK REDUNDANCY IN A MEMORY ARRAY 审中-公开
标题翻译：在存储阵列中加入块冗余的方法和装置
公开(公告)号：WO2006121529A2
公开(公告)日：2006-11-16
申请号：PCT/US2006/012107
申请日：2006-03-31
申请人： SANDISK 3D LLC , FASOLI, Luca, G. , SCHEUERLEIN, Roy, E.
发明人： FASOLI, Luca, G. , SCHEUERLEIN, Roy, E.
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C29/76 , G11C29/804 , G11C29/816
摘要： An integrated circuit memory array includes alternating first and second types of memory blocks, each memory block including respective array lines shared with a respective array line in an adjacent memory block. The array lines of a defective block of one type are mapped into a spare block of the same type. The array lines of a first adjacent block which are shared with array lines of the defective block, and the array lines of a second adjacent block which are shared with array lines of the defective block, are mapped into a second spare block of the other type, thereby mapping the defective block and portions of both adjacent blocks into just two spare blocks.
摘要翻译：集成电路存储器阵列包括交替的第一和第二类型的存储块，每个存储块包括与相邻存储器块中的相应阵列线共享的相应阵列线。一种类型的缺陷块的阵列线被映射到相同类型的备用块。与缺陷块的阵列线共享的第一相邻块的阵列线和与缺陷块的阵列线共享的第二相邻块的阵列线被映射到另一种类型的第二备用块从而将缺陷块和两个相邻块的部分映射到仅两个备用块中。

8. 发明申请

WO2006107409A2 DECODING CIRCUIT FOR NON-BINARY GROUPS OF MEMORY LINE DRIVERS 审中-公开
标题翻译：解码存储线驱动器非二进制组的电路
公开(公告)号：WO2006107409A2
公开(公告)日：2006-10-12
申请号：PCT/US2006/005067
申请日：2006-02-14
申请人： SANDISK , SCHEUERLEIN, Roy, E. , PETTI, Christopher, J. , FASOLI, Luca, G.
发明人： SCHEUERLEIN, Roy, E. , PETTI, Christopher, J. , FASOLI, Luca, G.
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C5/063 , G11C8/08 , G11C8/14
摘要： A decoding circuit for non-binary groups of memory line drivers is disclosed. In one embodiment, an integrated circuit is disclosed comprising a binary decoder and circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder. In another embodiment, an integrated circuit is disclosed comprising a memory array comprising a plurality of array lines, a non-integral-power-of-two number of array line driver circuits, and control circuitry configured to select one of the array line driver circuits. The control circuitry can comprise a binary decoder and a pre-decoder portion that performs a non-binary arithmetic operation. The concepts described herein may be used alone or in combination.
摘要翻译：公开了一种用于非二进制组的存储器线驱动器的解码电路。在一个实施例中，公开了一种集成电路，其包括二进制解码器和用于执行非二进制算术运算的电路，其中非二进制算术运算的结果被提供作为二进制解码器的输入。在另一个实施例中，公开了一种集成电路，其包括存储器阵列，该存储器阵列包括多个阵列线，两个非整数倍数的阵列线驱动器电路，以及控制电路，被配置为选择阵列线驱动电路之一。控制电路可以包括执行非二进制算术运算的二进制解码器和预解码器部分。本文所述的概念可以单独使用或组合使用。

9. 发明申请

WO2006105453A3 INTEGRATED CIRCUIT MEMORY ARRAY CONFIGURATION INCLUDING DECODING COMPATIBILITY WITH PARTIAL IMPLEMENTATION OF MULTIPLE MEMORY LAYERS 审中-公开
公开(公告)号：WO2006105453A3
公开(公告)日：2006-10-05
申请号：PCT/US2006/012106
申请日：2006-03-31
申请人： SANDISK 3D LLC , FASOLI, Luca, G. , SCHEUERLEIN, Roy, E.
发明人： FASOLI, Luca, G. , SCHEUERLEIN, Roy, E.
IPC分类号： G11C15/02 , G11C5/06 , G11C8/00
摘要： An integrated circuit having a three-dimensional memory array provides for a given number of memory planes (FIG. 15), but may be fabricated instead to include a lesser number of memory planes by omitting the masks and processing steps associated with the omitted memory planes, without changing any of the other fabrication mask for the other memory planes or for the remainder of the device, and without requiring routing or other configuration changes to the read or read/write path for the array. Control circuit for selectively enabling certain layer selector circuits is configurable (FIG. 33), and the layer selector circuits are suitably arranged , to couple a respective array line on an implemented memory layer to each respective I/O bus line irrespective of the number of implemented memory planes.

10. 发明申请

WO2009158673A1 SIMULTANEOUS WRITE AND VERIFY IN A NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储中同时写入和验证
公开(公告)号：WO2009158673A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048951
申请日：2009-06-26
申请人： SANDISK 3D LLC , FASOLI, Luca, G. , YAN, Tianhong , LEE, Jeffrey Koon, Yee
发明人： FASOLI, Luca, G. , YAN, Tianhong , LEE, Jeffrey Koon, Yee
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C16/3481 , G11C2013/0066 , G11C2213/32 , G11C2213/72
摘要： A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and resetting of the reversible resistance-switching elements.
摘要翻译：存储器系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储单元的三维存储器阵列（衬底上方），以及用于检测可逆电阻的设置和复位的电路开关元件

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