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1. 发明申请

US20110154006A1 MECHANISM FOR DETECTING A NO-PROCESSOR SWAP CONDITION AND MODIFICATION OF HIGH SPEED BUS CALIBRATION DURING BOOT 有权
标题翻译：检测无处理器交换条件的机制和引导期间高速公交校准的修改
公开(公告)号：US20110154006A1
公开(公告)日：2011-06-23
申请号：US12643108
申请日：2009-12-21
申请人： MAHESH S. NATU , John V. Lovelace , Rajesh P. Banginwar
发明人： MAHESH S. NATU , John V. Lovelace , Rajesh P. Banginwar
IPC分类号： G06F9/00
CPC分类号： G06F21/74 , G06F9/4403 , G06F21/44 , G06F21/575 , G06F21/71 , G06F21/73 , G06F21/85 , G06F2221/2105 , G06F2221/2129 , G06F2221/2149 , G06F2221/2153
摘要： Memory channel training parameters are function of electrical characteristics of memory devices, processor(s) and memory channel(s). Training steps can be skipped if the BIOS can determine that the memory devices, motherboard and processor have not changed since the last boot. Memory devices contain a serial number for tracking purposes and most motherboards contain a serial number. Many processors do not provide a mechanism by which the BIOS can track the processor. Described herein are techniques that allow the BIOS to track a processor and detect a swap without violating privacy/security requirements.
摘要翻译：存储器通道训练参数是存储器件，处理器和存储器通道的电特性的函数。如果BIOS可以确定自上次启动以来，内存设备，主板和处理器没有更改，则可跳过培训步骤。存储器件包含用于跟踪目的的序列号，并且大多数主板都包含序列号。许多处理器不提供BIOS可以跟踪处理器的机制。这里描述的是允许BIOS跟踪处理器并检测交换而不违反隐私/安全要求的技术。

2. 发明申请

US20140282502A1 LAYERED VIRTUAL MACHINE INTEGRITY MONITORING 有权
标题翻译：层层虚拟机完整性监控
公开(公告)号：US20140282502A1
公开(公告)日：2014-09-18
申请号：US13797924
申请日：2013-03-12
申请人： MAHESH S. NATU , SHAMANNA M. DATTA
发明人： MAHESH S. NATU , SHAMANNA M. DATTA
IPC分类号： G06F9/455
CPC分类号： G06F9/45533 , G06F9/45558 , G06F11/30 , G06F21/53 , G06F21/57 , G06F2009/45591
摘要： Various embodiments are generally directed to the provision and use of various hardware and software components of a computing device to monitor the state of layered virtual machine (VM) monitoring software components. An apparatus includes a first processor element; and logic to receive an indication that a first timer has reached an end of a first period of time, monitor execution of a VMM (virtual machine monitor) watcher by a second processor element, determine whether the second processor element completes execution of the VMM watcher to verify integrity of a VMM before a second timer reaches an end of a second period of time, and transmit an indication of the determination to a computing device. Other embodiments are described and claimed.
摘要翻译：各种实施例通常涉及提供和使用计算设备的各种硬件和软件组件来监视分层虚拟机（VM）监视软件组件的状态。一种装置包括：第一处理器元件; 以及用于接收第一定时器已经达到第一时间段结束的指示的逻辑，监视第二处理器元件执行VMM（虚拟机监视器）观察者，确定第二处理器元件是否完成VMM观察器的执行以在第二计时器到达第二时间段结束之前验证VMM的完整性，并将所述确定的指示传送到计算设备。描述和要求保护其他实施例。

3. 发明申请

US20100169729A1 ENABLING AN INTEGRATED MEMORY CONTROLLER TO TRANSPARENTLY WORK WITH DEFECTIVE MEMORY DEVICES 审中-公开
标题翻译：使用集成式存储器控制器来透明地处理有缺陷的存储器件
公开(公告)号：US20100169729A1
公开(公告)日：2010-07-01
申请号：US12345948
申请日：2008-12-30
申请人： SHAMANNA M. DATTA , JAMES W. ALEXANDER , MAHESH S. NATU , RAHUL KHANNA , MOHAN J. KUMAR
发明人： SHAMANNA M. DATTA , JAMES W. ALEXANDER , MAHESH S. NATU , RAHUL KHANNA , MOHAN J. KUMAR
IPC分类号： G06F11/07 , G06F15/177 , G11C5/06
CPC分类号： G11C29/50 , G11C5/04 , G11C29/028 , G11C29/46 , G11C29/50016 , G11C29/76 , G11C2029/0409 , G11C2029/0411 , G11C2029/5002 , G11C2029/5004 , G11C2029/5606
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for enabling an integrated memory controller to transparently work with defective memory devices. In some embodiments, a marginal condition is imposed on a memory module during normal operations of the memory module. The term “marginal condition” refers to a condition that is out of compliance with a specified (or “normal”) operating condition for the memory module. The memory module may exhibit failures in response to the marginal conditions and compensating mechanisms may mitigate the failures.
摘要翻译：本发明的实施例通常涉及用于使集成存储器控制器透明地与缺陷存储器件一起工作的系统，方法和装置。在一些实施例中，在存储器模块的正常操作期间，对存储器模块施加边际条件。术语“边缘条件”是指不符合内存模块的指定（或“正常”）操作条件的条件。存储器模块可能会出现响应边缘条件的故障，并且补偿机制可以减轻故障。

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