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1. 发明申请

US20050259685A1 Dual speed interface between media access control unit and physical unit 审中-公开
标题翻译：介质访问控制单元与物理单元之间的双速接口
公开(公告)号：US20050259685A1
公开(公告)日：2005-11-24
申请号：US10851002
申请日：2004-05-21
申请人： Luke Chang , Ilango Ganga
发明人： Luke Chang , Ilango Ganga
IPC分类号： H04J3/22 , H04L12/56 , H04W88/06
CPC分类号： H04W88/06
摘要： An apparatus, system, and method to provide a dual speed bi-directional link between a media access control (“MAC”) unit and a physical (“PHY”) unit. The MAC unit controls access to a physical medium and the PHY unit couples to the physical medium. A bi-directional link couples first transmit data paths (“TXDPs”) and first receive data paths (“RXDPs”) of the MAC unit to second TXDPs and second RXDPs of the PHY unit. The MAC and PHY units configured to route data along all of the first and second TXDPs and RXDPs during fast speed operation and to route the data along one of the first and second TXDPs and one of the first and second RXDPs during the slow speed operation.
摘要翻译：一种在介质访问控制（“MAC”）单元和物理（“PHY”）单元之间提供双速双向链路的装置，系统和方法。 MAC单元控制对物理介质的访问，并且PHY单元耦合到物理介质。双向链路将MAC单元的第一发送数据路径（“TXDP”）和第一接收数据路径（“RXDP”）耦合到PHY单元的第二TXDP和第二RXDP。 MAC和PHY单元被配置为在快速操作期间沿着所有第一和第二TXDP和RXDP路由数据，并且在慢速操作期间沿着第一和第二TXDP以及第一和第二RXDP之一路由数据。

2. 发明申请

US20050111531A1 System, method and device for autonegotiation 有权
标题翻译：用于自动协商的系统，方法和设备
公开(公告)号：US20050111531A1
公开(公告)日：2005-05-26
申请号：US10801504
申请日：2004-03-15
申请人： Bradley Booth , Luke Chang , Ilango Ganga
发明人： Bradley Booth , Luke Chang , Ilango Ganga
IPC分类号： H04L12/407 , H04L12/46 , B41B1/00
CPC分类号： H04L12/4625 , H04L12/40136
摘要： Disclosed are a system, method and device for negotiating a data transmission mode over an attachment unit interface (DDI). A data transceiver circuit may be coupled to one or more data lanes of the DDI. A negotiation section may receive a link pulse signal on at least one data lane in the DDI during a negotiation period and selectively configure the data transceiver to transmit and receive data on one or more data lanes according to a data transmission mode based upon the received link pulse signal.
摘要翻译：公开了一种用于通过附件单元接口（DDI）协商数据传输模式的系统，方法和设备。数据收发器电路可以耦合到DDI的一个或多个数据通道。协商部分可以在协商期间在DDI中的至少一个数据通道上接收链路脉冲信号，并且基于所接收的链路，根据数据传输模式选择性地配置数据收发器在一个或多个数据通道上发送和接收数据脉冲信号。

3. 发明申请

US20070157060A1 Techniques to perform forward error correction for an electrical backplane 有权
标题翻译：对电气背板进行前向纠错的技术
公开(公告)号：US20070157060A1
公开(公告)日：2007-07-05
申请号：US11325765
申请日：2006-01-04
申请人： Ilango Ganga , Luke Chang , Andrey Belogolovy , Andrei Ovchinnikov
发明人： Ilango Ganga , Luke Chang , Andrey Belogolovy , Andrei Ovchinnikov
IPC分类号： H03M13/00
CPC分类号： H04L1/0043 , G06F11/10 , H03M13/33 , H03M13/63 , H03M13/6312 , H04L1/0041 , H04L1/0042 , H04L1/0047 , H04L1/0057 , H04L1/0058 , H04L1/0072 , H04L7/041 , Y02D30/32
摘要： Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. Other embodiments are described and claimed.
摘要翻译：描述了用于执行电背板的前向纠错的技术。装置可以包括具有前向纠错子层的物理层单元，以使用单个位来执行前向纠错来表示两位同步头。描述和要求保护其他实施例。

4. 发明申请

US20050271064A1 Dual speed interface between media access control unit and physical unit 失效
标题翻译：介质访问控制单元与物理单元之间的双速接口
公开(公告)号：US20050271064A1
公开(公告)日：2005-12-08
申请号：US11020945
申请日：2004-12-23
申请人： Luke Chang , Ilango Ganga
发明人： Luke Chang , Ilango Ganga
IPC分类号： H04J3/22 , H04L12/56 , H04W88/06
CPC分类号： H04W88/06 , H04L69/14 , H04L69/32
摘要： A system and method to implement a dual speed network interface. A first code is transmitted from an initiator unit to a follower unit on a first output datapath (“OUT_DP”) of multiple OUT_DPs coupling the initiator unit to the follower unit. The first code is transmitted to initiate a speed change of a link to a physical medium for communicating data. The first code is transmitted at a first datapath speed. A second code is received on a first input datapath (“IN_DP”) of multiple IN_DPs coupling the follower unit to the initiator unit. The second code indicates to the initiator unit that the follower unit received the first code. The first OUT_DP is then placed into an idle state in response to receiving the second code. Subsequently, the first OUT_DP is enabled after the idle state at a second datapath speed different from the first datapath speed.
摘要翻译：一种实现双速网络接口的系统和方法。第一代码在从启动器单元耦合到跟随单元的多个OUT_DP的第一输出数据路径（“OUT_DP”）上从发起者单元发送到跟随单元。传送第一代码以启动到用于传送数据的物理介质的链接的速度改变。第一个代码以第一个数据路径速度传输。第二代码在多个IN_DP的第一输入数据路径（“IN_DP”）上被接收，该IN_DP将从动单元耦合到发起者单元。第二代码向发起者单元指示跟随单元接收到第一代码。响应于接收第二代码，第一个OUT_DP被置于空闲状态。随后，在与第一数据路径速度不同的第二数据路径速度的空闲状态之后，第一个OUT_DP被使能。

5. 发明申请

US20140181394A1 DIRECTORY CACHE SUPPORTING NON-ATOMIC INPUT/OUTPUT OPERATIONS 有权
标题翻译：目录缓存支持非原始输入/输出操作
公开(公告)号：US20140181394A1
公开(公告)日：2014-06-26
申请号：US13724214
申请日：2012-12-21
申请人： Herbert H. Hum , James R. Vash , Eric A. Gouldey , Ganesh Kumar , David Bubien , Manoj K. Arora , Luke Chang , Lavanya Nama , Mahak Gupta
发明人： Herbert H. Hum , James R. Vash , Eric A. Gouldey , Ganesh Kumar , David Bubien , Manoj K. Arora , Luke Chang , Lavanya Nama , Mahak Gupta
IPC分类号： G06F12/08
CPC分类号： G06F12/082 , G06F12/0824 , G06F12/0833 , G06F12/0835 , G06F2212/1016 , G06F2212/621
摘要： Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor.
摘要翻译：响应于从输入/输出设备接收对高速缓存线的写入请求，第一处理器的高速缓存代理器确定高速缓存行由第二处理器的归属代理管理。缓存代理向第二处理器发送高速缓存行的所有权请求。第二处理器的归属代理接收所有权请求，在高速缓存行的目录高速缓存中生成条目，将远程高速缓存代理标识为具有高速缓存行的所有权的条目，并将高速缓存行的所有权授予远程缓存代理商响应于从所述归属代理接收对所述高速缓存行的所有权的许可，所述第一处理器的输入/输出控制器将用于所述高速缓存行的条目添加到输入/输出写入高速缓存，所述条目包括所述高速缓存行是由第二处理器的归属代理管理。

6. 发明申请

US20140115223A1 DUAL CASTING PCIE INBOUND WRITES TO MEMORY AND PEER DEVICES 有权
标题翻译：双重写入到记忆和对等设备的写入
公开(公告)号：US20140115223A1
公开(公告)日：2014-04-24
申请号：US13656134
申请日：2012-10-19
申请人： Jayakrishna Guddeti , Luke Chang
发明人： Jayakrishna Guddeti , Luke Chang
IPC分类号： G06F13/36
CPC分类号： G06F13/404 , G06F13/14 , G06F2213/0026
摘要： Methods and apparatus for supporting dual casting of inbound system memory writes from PCIe devices to memory and a peer PCIe device. An inbound system memory write request from a first PCIe device is received at a PCIe root complex and the memory address is inspected to determine whether it falls within an address window defined for dual casting operations. If it does, an IO write request is generated from the inbound system memory write request and sent to a second PCIe device associated with the address window. During a parallel operation, the original inbound system memory write request is forwarded to a system agent configured to receive such write requests.
摘要翻译：用于支持从PCIe设备到存储器和对等PCIe设备的入站系统存储器双向注入的方法和设备。在PCIe根组合处接收来自第一PCIe设备的入站系统存储器写入请求，并检查存储器地址以确定其是否落入为双重铸造操作定义的地址窗口内。如果是这样，则从入站系统存储器写请求产生IO写请求，并将其发送到与地址窗口相关联的第二PCIe设备。在并行操作期间，将原始入站系统内存写请求转发给配置为接收此类写请求的系统代理。

7. 发明授权

US07885321B2 System, method and device for autonegotiation 有权
标题翻译：用于自动协商的系统，方法和设备
公开(公告)号：US07885321B2
公开(公告)日：2011-02-08
申请号：US12752370
申请日：2010-04-01
申请人： Bradley J. Booth , Luke Chang , Ilango S. Ganga
发明人： Bradley J. Booth , Luke Chang , Ilango S. Ganga
IPC分类号： H04B1/38
CPC分类号： H04L12/4625 , H04L12/40136
摘要： Disclosed are a system, method and device for negotiating a data transmission mode over an attachment unit interface (DDI). A data transceiver circuit may be coupled to one or more data lanes of the DDI. A negotiation section may receive a link pulse signal on at least one data lane in the DDI during a negotiation period and selectively configure the data transceiver to transmit and receive data on one or more data lanes according to a data transmission mode based upon the received link pulse signal.
摘要翻译：公开了一种用于通过附件单元接口（DDI）协商数据传输模式的系统，方法和设备。数据收发器电路可以耦合到DDI的一个或多个数据通道。协商部分可以在协商期间在DDI中的至少一个数据通道上接收链路脉冲信号，并且基于所接收的链路，根据数据传输模式选择性地配置数据收发器在一个或多个数据通道上发送和接收数据脉冲信号。

8. 发明授权

US07676733B2 Techniques to perform forward error correction for an electrical backplane 有权
标题翻译：对电气背板进行前向纠错的技术
公开(公告)号：US07676733B2
公开(公告)日：2010-03-09
申请号：US11325765
申请日：2006-01-04
申请人： Ilango S. Ganga , Luke Chang , Andrey Belogolovy , Andrei Ovchinnikov
发明人： Ilango S. Ganga , Luke Chang , Andrey Belogolovy , Andrei Ovchinnikov
IPC分类号： H03M13/00
CPC分类号： H04L1/0043 , G06F11/10 , H03M13/33 , H03M13/63 , H03M13/6312 , H04L1/0041 , H04L1/0042 , H04L1/0047 , H04L1/0057 , H04L1/0058 , H04L1/0072 , H04L7/041 , Y02D30/32
摘要： Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.
摘要翻译：描述了用于执行电背板的前向纠错的技术。一种装置包括具有前向纠错子层的物理层单元，以使用单个位执行前向纠错来表示两位同步头。

9. 发明授权

US07668194B2 Dual speed interface between media access control unit and physical unit 失效
标题翻译：介质访问控制单元与物理单元之间的双速接口
公开(公告)号：US07668194B2
公开(公告)日：2010-02-23
申请号：US11020945
申请日：2004-12-23
申请人： Luke Chang , Ilango S. Ganga
发明人： Luke Chang , Ilango S. Ganga
IPC分类号： H04J3/16 , H04J3/00
CPC分类号： H04W88/06 , H04L69/14 , H04L69/32
摘要： A system and method to implement a dual speed network interface. A first code is transmitted from an initiator unit to a follower unit on a first output datapath (“OUT_DP”) of multiple OUT_DPs coupling the initiator unit to the follower unit. The first code is transmitted to initiate a speed change of a link to a physical medium for communicating data. The first code is transmitted at a first datapath speed. A second code is received on a first input datapath (“IN_DP”) of multiple IN_DPs coupling the follower unit to the initiator unit. The second code indicates to the initiator unit that the follower unit received the first code. The first OUT_DP is then placed into an idle state in response to receiving the second code. Subsequently, the first OUT_DP is enabled after the idle state at a second datapath speed different from the first datapath speed.
摘要翻译：一种实现双速网络接口的系统和方法。第一代码在从启动器单元耦合到跟随单元的多个OUT_DP的第一输出数据路径（“OUT_DP”）上从发起者单元发送到跟随单元。传送第一代码以启动到用于传送数据的物理介质的链接的速度改变。第一个代码以第一个数据路径速度传输。第二代码在多个IN_DP的第一输入数据路径（“IN_DP”）上被接收，该IN_DP将从动单元耦合到发起者单元。第二代码向发起者单元指示跟随单元接收到第一代码。响应于接收第二代码，第一个OUT_DP被置于空闲状态。随后，在与第一数据路径速度不同的第二数据路径速度的空闲状态之后，第一个OUT_DP被使能。

10. 发明申请

US20050135433A1 System and method using a packetized encoded bitstream for parallel compression and decompression 失效
标题翻译：使用分组编码比特流进行并行压缩和解压缩的系统和方法
公开(公告)号：US20050135433A1
公开(公告)日：2005-06-23
申请号：US11039771
申请日：2005-01-19
申请人： Luke Chang , Michael Fuccio , John Liu , Gordon Elder
发明人： Luke Chang , Michael Fuccio , John Liu , Gordon Elder
IPC分类号： H04J3/04 , H04L12/28 , H04L12/56 , H04N7/26 , H04N7/30
CPC分类号： H04N19/436 , H04N19/176 , H04N19/186 , H04N19/60
摘要： A system and method are disclosed for parallel compression and decompression of a bitstream. For compression, the bitstream is separated into a plurality of components, and the components are encoded using a compression algorithm. Packets are then constructed from the encoded components. At least one packet is associated with each encoded component and comprises header information and encoded data. The packets are combined into a packetized encoded bitstream. For decompression, the packets are separated from the packetized encoded bitstream using the header information. The packets are then decoded in parallel using a decompression algorithm to recover the encoded data. The plurality of components are reconstructed from the recovered encoded data and combined to-recover the bitstream.
摘要翻译：公开了用于比特流的并行压缩和解压缩的系统和方法。为了压缩，将比特流分成多个组件，并且使用压缩算法对组件进行编码。然后从编码的组件构建包。至少一个分组与每个编码的分量相关联并且包括报头信息和编码数据。分组被组合成分组化的编码比特流。对于解压缩，使用报头信息将分组与分组化的编码比特流分离。然后使用解压缩算法并行解码分组以恢复编码数据。从恢复的编码数据重建多个分量，并组合以恢复比特流。

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