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1. 发明申请

US20130015579A1 SOLDER BALL CONTACT SUSCEPTIBLE TO LOWER STRESS 有权
标题翻译：焊球接触不牢固到下压
公开(公告)号：US20130015579A1
公开(公告)日：2013-01-17
申请号：US13615804
申请日：2012-09-14
申请人： Luc Guerin , Mario J. Interrante , Michael J. Shapiro , Thuy Tran-Quinn , Van T. Truong
发明人： Luc Guerin , Mario J. Interrante , Michael J. Shapiro , Thuy Tran-Quinn , Van T. Truong
IPC分类号： H01L23/488
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02166 , H01L2224/03462 , H01L2224/03618 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05572 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/05681 , H01L2224/10126 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13022 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13139 , H01L2224/13147 , H01L2924/00014 , H01L2924/01074 , H01L2924/01029 , H01L2924/01028 , H01L2924/01026 , H01L2224/05552
摘要： A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.
摘要翻译：焊球接触和制造焊球接触的方法包括：在集成电路（IC）芯片和金属焊盘上形成有通孔的第一绝缘层; 设置在所述通孔内和所述第一绝缘层的围绕所述通孔的部分上的凸块下冶金（UBM）结构; 第二绝缘层，形成在所述UBM结构的位于所述通孔的中心的外部的上表面上; 以及填充通孔并且设置在UBM结构的与通孔接触的内部的上表面上方的焊球，其中在焊球下面的UBM结构具有比焊球更大的直径。

2. 发明申请

US20120256313A1 SOLDER BALL CONTACT SUSCEPTIBLE TO LOWER STRESS 有权
标题翻译：焊球接触不牢固到下压
公开(公告)号：US20120256313A1
公开(公告)日：2012-10-11
申请号：US13080105
申请日：2011-04-05
申请人： Luc Guerin , Mario J. Interrante , Michael J. Shapiro , Thuy Tran-Quinn , Van T. Truong
发明人： Luc Guerin , Mario J. Interrante , Michael J. Shapiro , Thuy Tran-Quinn , Van T. Truong
IPC分类号： H01L23/498 , H01L21/28
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02166 , H01L2224/03462 , H01L2224/03618 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05572 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/05681 , H01L2224/10126 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13022 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13139 , H01L2224/13147 , H01L2924/00014 , H01L2924/01074 , H01L2924/01029 , H01L2924/01028 , H01L2924/01026 , H01L2224/05552
摘要： A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.
摘要翻译：焊球接触和制造焊球接触的方法包括：在集成电路（IC）芯片和金属焊盘上形成有通孔的第一绝缘层; 设置在所述通孔内和所述第一绝缘层的围绕所述通孔的部分上的凸块下冶金（UBM）结构; 第二绝缘层，形成在所述UBM结构的位于所述通孔的中心的外部的上表面上; 以及填充通孔并且设置在UBM结构的与通孔接触的内部的上表面上方的焊球，其中在焊球下面的UBM结构具有比焊球更大的直径。

3. 发明授权

US08614512B2 Solder ball contact susceptible to lower stress 有权
公开(公告)号：US08614512B2
公开(公告)日：2013-12-24
申请号：US13615804
申请日：2012-09-14
申请人： Luc Guerin , Mario J. Interrante , Michael J. Shapiro , Thuy Tran-Quinn , Van T. Truong
发明人： Luc Guerin , Mario J. Interrante , Michael J. Shapiro , Thuy Tran-Quinn , Van T. Truong
IPC分类号： H01L29/40
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02166 , H01L2224/03462 , H01L2224/03618 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05572 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/05681 , H01L2224/10126 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13022 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13139 , H01L2224/13147 , H01L2924/00014 , H01L2924/01074 , H01L2924/01029 , H01L2924/01028 , H01L2924/01026 , H01L2224/05552
摘要： A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

4. 发明授权

US08383505B2 Solder ball contact susceptible to lower stress 有权
标题翻译：焊球接触容易受到较低的应力
公开(公告)号：US08383505B2
公开(公告)日：2013-02-26
申请号：US13080105
申请日：2011-04-05
申请人： Luc Guerin , Mario J. Interrante , Michael J. Shapiro , Thuy Tran-Quinn , Van T. Truong
发明人： Luc Guerin , Mario J. Interrante , Michael J. Shapiro , Thuy Tran-Quinn , Van T. Truong
IPC分类号： H01L21/00
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02166 , H01L2224/03462 , H01L2224/03618 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05572 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/05681 , H01L2224/10126 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13022 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13139 , H01L2224/13147 , H01L2924/00014 , H01L2924/01074 , H01L2924/01029 , H01L2924/01028 , H01L2924/01026 , H01L2224/05552
摘要： A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.
摘要翻译：焊球接触和制造焊球接触的方法包括：在集成电路（IC）芯片和金属焊盘上形成有通孔的第一绝缘层; 设置在所述通孔内和所述第一绝缘层的围绕所述通孔的部分上的凸块下冶金（UBM）结构; 第二绝缘层，形成在所述UBM结构的位于所述通孔的中心的外部的上表面上; 以及填充通孔并且设置在UBM结构的与通孔接触的内部的上表面上方的焊球，其中在焊球下面的UBM结构具有比焊球更大的直径。

5. 发明授权

US08487447B2 Semiconductor structure having offset passivation to reduce electromigration 有权
标题翻译：具有偏移钝化以减少电迁移的半导体结构
公开(公告)号：US08487447B2
公开(公告)日：2013-07-16
申请号：US13111283
申请日：2011-05-19
申请人： Mario J. Interrante , Gary LaFontant , Michael J. Shapiro , Thomas A. Wassick , Bucknell C. Webb
发明人： Mario J. Interrante , Gary LaFontant , Michael J. Shapiro , Thomas A. Wassick , Bucknell C. Webb
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/3171 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/02163 , H01L2224/0401 , H01L2224/05147 , H01L2224/05551 , H01L2224/0557 , H01L2224/05571 , H01L2224/05647 , H01L2224/0569 , H01L2224/06131 , H01L2224/06134 , H01L2224/13005 , H01L2224/13016 , H01L2224/13022 , H01L2224/13025 , H01L2224/13026 , H01L2224/13028 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/014 , H01L2924/15311 , H01L2924/049 , H01L2924/053 , H01L2224/05552
摘要： A semiconductor structure which includes a plurality of stacked semiconductor chips in a three dimensional configuration. There is a first semiconductor chip in contact with a second semiconductor chip. The first semiconductor chip includes a through silicon via (TSV) extending through the first semiconductor chip; an electrically conducting pad at a surface of the first semiconductor chip, the TSV terminating in contact at a first side of the electrically conducting pad; a passivation layer covering the electrically conducting pad, the passivation layer having a plurality of openings; and a plurality of electrically conducting structures formed in the plurality of openings and in contact with a second side of the electrically conducting pad, the contact of the plurality of electrically conducting structures with the electrically conducting pad being offset with respect to the contact of the TSV with the electrically conducting pad.
摘要翻译：一种半导体结构，其包括三维结构中的多个层叠半导体芯片。存在与第二半导体芯片接触的第一半导体芯片。第一半导体芯片包括延伸穿过第一半导体芯片的贯穿硅通孔（TSV）; 在所述第一半导体芯片的表面处的导电焊盘，所述TSV终止于所述导电焊盘的第一侧接触; 覆盖所述导电焊盘的钝化层，所述钝化层具有多个开口; 以及形成在所述多个开口中并与所述导电垫的第二侧接触的多个导电结构，所述多个导电结构与所述导电垫的接触相对于所述TSV的接触而偏移与导电垫。

6. 发明申请

US20120292779A1 SEMICONDUCTOR STRUCTURE HAVING OFFSET PASSIVATION TO REDUCE ELECTROMIGRATION 有权
标题翻译：半导体结构具有减少电磁偏移的局限性
公开(公告)号：US20120292779A1
公开(公告)日：2012-11-22
申请号：US13111283
申请日：2011-05-19
申请人： MARIO J. INTERRANTE , Gary LaFontant , Michael J. Shapiro , Thomas A. Wassick , Bucknell C. Webb
发明人： MARIO J. INTERRANTE , Gary LaFontant , Michael J. Shapiro , Thomas A. Wassick , Bucknell C. Webb
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L23/3171 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/02163 , H01L2224/0401 , H01L2224/05147 , H01L2224/05551 , H01L2224/0557 , H01L2224/05571 , H01L2224/05647 , H01L2224/0569 , H01L2224/06131 , H01L2224/06134 , H01L2224/13005 , H01L2224/13016 , H01L2224/13022 , H01L2224/13025 , H01L2224/13026 , H01L2224/13028 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/014 , H01L2924/15311 , H01L2924/049 , H01L2924/053 , H01L2224/05552
摘要： A semiconductor structure which includes a plurality of stacked semiconductor chips in a three dimensional configuration. There is a first semiconductor chip in contact with a second semiconductor chip. The first semiconductor chip includes a through silicon via (TSV) extending through the first semiconductor chip; an electrically conducting pad at a surface of the first semiconductor chip, the TSV terminating in contact at a first side of the electrically conducting pad; a passivation layer covering the electrically conducting pad, the passivation layer having a plurality of openings; and a plurality of electrically conducting structures formed in the plurality of openings and in contact with a second side of the electrically conducting pad, the contact of the plurality of electrically conducting structures with the electrically conducting pad being offset with respect to the contact of the TSV with the electrically conducting pad.
摘要翻译：一种半导体结构，其包括三维结构中的多个层叠半导体芯片。存在与第二半导体芯片接触的第一半导体芯片。第一半导体芯片包括延伸穿过第一半导体芯片的贯穿硅通孔（TSV）; 在所述第一半导体芯片的表面处的导电焊盘，所述TSV终止于所述导电焊盘的第一侧接触; 覆盖所述导电焊盘的钝化层，所述钝化层具有多个开口; 以及形成在所述多个开口中并与所述导电垫的第二侧接触的多个导电结构，所述多个导电结构与所述导电垫的接触相对于所述TSV的接触而偏移与导电垫。

7. 发明授权

US09105627B2 Coil inductor for on-chip or on-chip stack 有权
标题翻译：用于片上或片上堆叠的线圈电感
公开(公告)号：US09105627B2
公开(公告)日：2015-08-11
申请号：US13289071
申请日：2011-11-04
申请人： Michael J. Shapiro , Gary D. Carpenter , Alan J. Drake , Rachel Gordin , Edmund J. Sprogis
发明人： Michael J. Shapiro , Gary D. Carpenter , Alan J. Drake , Rachel Gordin , Edmund J. Sprogis
IPC分类号： H01F5/00 , H01L27/08 , H01L23/498 , H01L23/522 , H01L23/64 , H01L49/02 , H01F17/00 , H01F41/00
CPC分类号： H01L23/49822 , H01F17/0013 , H01F41/005 , H01F2017/0086 , H01L23/5227 , H01L23/645 , H01L28/10 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/01322 , H01L2924/15311 , H01L2924/30107 , H01L2924/00
摘要： A coil inductor and buck voltage regulator incorporating the coil inductor are provided which can be fabricated on a microelectronic element such as a semiconductor chip, or on an interconnection element such as a semiconductor, glass or ceramic interposer element. When energized, the coil inductor has magnetic flux extending in a direction parallel to first and second opposed surfaces of the microelectronic or interconnection element, and whose peak magnetic flux is disposed between the first and second surfaces. In one example, the coil inductor can be formed by first conductive lines extending along the first surface of the microelectronic or interconnection element, second conductive lines extending along the second surface of the microelectronic or interconnection element, and a plurality of conductive vias, e.g., through silicon vias, extending in direction of a thickness of the microelectronic or interconnection element. A method of making the coil inductor is also provided.
摘要翻译：提供了一种结合线圈电感器的线圈电感器和降压稳压器，其可以制造在诸如半导体芯片的微电子元件上，或者在诸如半导体，玻璃或陶瓷插入元件的互连元件上。当通电时，线圈电感器具有沿平行于微电子或互连元件的第一和第二相对表面的方向延伸的磁通量，并且其峰值磁通量设置在第一和第二表面之间。在一个示例中，线圈电感器可以由沿着微电子或互连元件的第一表面延伸的第一导线形成，沿着微电子或互连元件的第二表面延伸的第二导电线，以及多个导电通孔，通过硅通孔，在微电子或互连元件的厚度方向上延伸。还提供了制造线圈电感器的方法。

8. 发明授权

US08495342B2 Configuring plural cores to perform an instruction having a multi-core characteristic 有权
标题翻译：配置多个内核以执行具有多核特性的指令
公开(公告)号：US08495342B2
公开(公告)日：2013-07-23
申请号：US12335921
申请日：2008-12-16
申请人： Louis B. Capps, Jr. , Michael J. Shapiro , Robert H. Bell, Jr. , Thomas E. Cook , William E. Burky
发明人： Louis B. Capps, Jr. , Michael J. Shapiro , Robert H. Bell, Jr. , Thomas E. Cook , William E. Burky
IPC分类号： G06F9/30
CPC分类号： G06F9/5061 , G06F9/3842 , G06F9/3851 , G06F9/3887
摘要： A processor having multiple cores coordinates functions performed on the cores to automatically, dynamically and repeatedly reconfigure the cores for optimal performance based on characteristics of currently executing software. A core running a thread detects a multi-core characteristic of the thread and assigns one or more other cores to the thread to dynamically combine the cores into what functionally amounts to a common core for more efficient execution of the thread.
摘要翻译：具有多个核的处理器协调在核上执行的功能，以基于当前执行的软件的特性自动，动态地和重复地重新配置核以获得最佳性能。运行线程的核心检测线程的多核特性，并为线程分配一个或多个其他内核，以将内核动态组合到功能上相当于共同核心的内核，从而更有效地执行线程。

9. 发明授权

US08299584B2 Alignment of wafers for 3D integration 有权
标题翻译：用于3D集成的晶片对齐
公开(公告)号：US08299584B2
公开(公告)日：2012-10-30
申请号：US12719241
申请日：2010-03-08
申请人： Dmitriy Shneyder , Srinivasan Rangarajan , Michael J. Shapiro , Anthony K. Stamper , Huilong Zhu
发明人： Dmitriy Shneyder , Srinivasan Rangarajan , Michael J. Shapiro , Anthony K. Stamper , Huilong Zhu
IPC分类号： H01L23/48
CPC分类号： B32B38/00 , G01B11/27 , G01J3/02 , G06F15/00 , H01L23/48 , H01L2924/0002 , H01L2924/00
摘要： A method of aligning substrates, e.g., semiconductor wafers, is provided in which a first substrate can be at least coarsely aligned atop a second substrate. Each substrate can have a pattern thereon, wherein the pattern of the first substrate can be aligned with a window of the first substrate. A return signal can be returned from simultaneously illuminating the patterns of the first and second substrates through the window in the first substrate. The return signal can be compared to at least one stored signal to determine relative misalignment between the first and second substrates. A position of at least one of the first and second substrates can be altered relative to a position of the other of the first and second substrates to address the misalignment.
摘要翻译：提供了对准例如半导体晶片的衬底的方法，其中第一衬底可以至少在第二衬底的顶部上对齐。每个衬底可以具有其上的图案，其中第一衬底的图案可以与第一衬底的窗口对准。可以通过第一衬底中的窗口同时照亮第一和第二衬底的图案来返回返回信号。可以将返回信号与至少一个存储的信号进行比较，以确定第一和第二基板之间的相对不对准。可以相对于第一和第二基板中的另一个的位置改变第一和第二基板中的至少一个的位置，以解决未对准。

10. 发明申请

US20090177445A1 Design Structure For An Apparatus For Monitoring And Controlling Heat Generation In A Multi-Core Processor 有权
标题翻译：用于监测和控制多核处理器中发热的装置的设计结构
公开(公告)号：US20090177445A1
公开(公告)日：2009-07-09
申请号：US12347947
申请日：2008-12-31
申请人： Louis Bennie Capps, JR. , Warren D. Dyckman , Michael J. Shapiro
发明人： Louis Bennie Capps, JR. , Warren D. Dyckman , Michael J. Shapiro
IPC分类号： G06F17/50
CPC分类号： G06F1/206
摘要： A design structure for a processor may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may control heat generation in a multi-core processor. The design structure may specify that each processor core includes a temperature sensor that reports temperature information to a processor controller. The design structure may also specify that if a particular processor core exceeds a predetermined temperature, the processor controller disables that processor core to allow that processor core to cool. The design structure may also specify that the processor controller enables the previously disabled processor core when the previously disabled processor core cools sufficiently to a normal operating temperature. In this manner, a multi-core processor may avoid undesirable hot spots that impact processor life.
摘要翻译：用于处理器的设计结构可以体现在用于设计，制造或测试处理器集成电路的机器可读介质中。该设计结构可以控制多核处理器中的发热。设计结构可以指定每个处理器核心包括向处理器控制器报告温度信息的温度传感器。该设计结构还可以指定如果特定处理器核心超过预定温度，则处理器控制器禁止该处理器核心使该处理器核心冷却。设计结构还可以指定当先前禁用的处理器核心充分冷却至正常工作温度时，处理器控制器启用先前禁用的处理器核心。以这种方式，多核处理器可以避免影响处理器寿命的不期望的热点。

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