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1. 发明申请

US20080157395A1 INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING IMPROVED REACTION BARRIER LAYERS 有权
标题翻译：使用无铅焊盘和改进的反应障碍层进行片芯互连
公开(公告)号：US20080157395A1
公开(公告)日：2008-07-03
申请号：US11616919
申请日：2006-12-28
申请人： Luc Belanger , Stephen L. Buchwalter , Leena Paivikki Buchwalter , Ajay P. Giri , Jonathan H. Griffith , Donald W. Henderson , Sung Kwon Kang , Eric H. Laine , Christian Lavoie , Paul A. Lauro , Valerie Anne Oberson , Da-Yuan Shih , Kamalesh K. Srivastava , Michael J. Sullivan
发明人： Luc Belanger , Stephen L. Buchwalter , Leena Paivikki Buchwalter , Ajay P. Giri , Jonathan H. Griffith , Donald W. Henderson , Sung Kwon Kang , Eric H. Laine , Christian Lavoie , Paul A. Lauro , Valerie Anne Oberson , Da-Yuan Shih , Kamalesh K. Srivastava , Michael J. Sullivan
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L24/12 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05599 , H01L2224/114 , H01L2224/11462 , H01L2224/1147 , H01L2224/116 , H01L2224/11849 , H01L2224/119 , H01L2224/13023 , H01L2224/13111 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/30107 , H01L2924/01083 , H01L2924/01049 , H01L2224/13099
摘要： An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.
摘要翻译：一种适于将微电子器件芯片倒装连接到封装的互连结构，包括二层，三层或四层限流冶金，包括粘附/反应阻挡层，并且具有与含锡的组分反应的焊料可湿性层无铅焊料，使得可焊接层在焊接期间可以完全消耗，但在焊接期间与无铅焊料接触后，阻挡层保持不变。一个或多个无铅焊料球选择性地位于焊料润湿层上，该无铅焊球包含锡作为主要成分和一种或多种合金成分。

2. 发明授权

US08314500B2 Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers 有权
标题翻译：用于使用无铅焊料的倒装芯片的互连并具有改进的反应阻挡层
公开(公告)号：US08314500B2
公开(公告)日：2012-11-20
申请号：US11616919
申请日：2006-12-28
申请人： Luc Belanger , Stephen L. Buchwalter , Leena Paivikki Buchwalter , Ajay P. Giri , Jonathan H. Griffith , Donald W. Henderson , Sung Kwon Kang , Eric H. Laine , Christian Lavoie , Paul A. Lauro , Valérie Anne Oberson , Da-Yuan Shih , Kamalesh K Srivastava , Michael J. Sullivan
发明人： Luc Belanger , Stephen L. Buchwalter , Leena Paivikki Buchwalter , Ajay P. Giri , Jonathan H. Griffith , Donald W. Henderson , Sung Kwon Kang , Eric H. Laine , Christian Lavoie , Paul A. Lauro , Valérie Anne Oberson , Da-Yuan Shih , Kamalesh K Srivastava , Michael J. Sullivan
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/12 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05599 , H01L2224/114 , H01L2224/11462 , H01L2224/1147 , H01L2224/116 , H01L2224/11849 , H01L2224/119 , H01L2224/13023 , H01L2224/13111 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/30107 , H01L2924/01083 , H01L2924/01049 , H01L2224/13099
摘要： An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.
摘要翻译：一种适于将微电子器件芯片倒装连接到封装的互连结构，包括二层，三层或四层限流冶金，包括粘附/反应阻挡层，并且具有与含锡的组分反应的焊料可湿性层无铅焊料，使得可焊接层在焊接期间可以完全消耗，但在焊接期间与无铅焊料接触后，阻挡层保持不变。一个或多个无铅焊料球选择性地位于焊料润湿层上，该无铅焊球包含锡作为主要成分和一种或多种合金成分。

3. 发明申请

US20100062597A1 Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers 有权
标题翻译：使用无铅焊料进行倒装芯片的互连并具有改进的反应阻挡层
公开(公告)号：US20100062597A1
公开(公告)日：2010-03-11
申请号：US12587301
申请日：2009-10-05
申请人： Luc Belanger , Stephen L. Buchwalter , Leena Paivikki Buchwalter , Ajay P. Giri , Jonathan H. Griffith , Donald W. Henderson , Sung Kwon Kang , Eric H. Laine , Christian Lavoie , Paul A. Lauro , Valérie Anne Oberson , Da-Yuan Shih , Kamalesh K. Srivastava , Michael J. Sullivan
发明人： Luc Belanger , Stephen L. Buchwalter , Leena Paivikki Buchwalter , Ajay P. Giri , Jonathan H. Griffith , Donald W. Henderson , Sung Kwon Kang , Eric H. Laine , Christian Lavoie , Paul A. Lauro , Valérie Anne Oberson , Da-Yuan Shih , Kamalesh K. Srivastava , Michael J. Sullivan
IPC分类号： H01L21/60
CPC分类号： H01L24/12 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05599 , H01L2224/114 , H01L2224/11462 , H01L2224/1147 , H01L2224/116 , H01L2224/11849 , H01L2224/119 , H01L2224/13023 , H01L2224/13111 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/30107 , H01L2924/01083 , H01L2924/01049 , H01L2224/13099
摘要： An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.
摘要翻译：一种适于将微电子器件芯片倒装连接到封装的互连结构，包括二层，三层或四层限流冶金，包括粘附/反应阻挡层，并且具有与含锡的组分反应的焊料可湿性层无铅焊料，使得可焊接层在焊接期间可以完全消耗，但在焊接期间与无铅焊料接触后，阻挡层保持不变。一个或多个无铅焊料球选择性地位于焊料润湿层上，该无铅焊球包含锡作为主要成分和一种或多种合金成分。

4. 发明授权

US07932169B2 Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers 有权
标题翻译：使用无铅焊料进行倒装芯片的互连并具有改进的反应阻挡层
公开(公告)号：US07932169B2
公开(公告)日：2011-04-26
申请号：US12587301
申请日：2009-10-05
申请人： Luc Belanger , Stephen L. Buchwalter , Leena Paivikki Buchwalter , Ajay P. Giri , Jonathan H. Griffith , Donald W. Henderson , Sung Kwon Kang , Eric H. Laine , Christian Lavoie , Paul A. Lauro , Valérie Anne Oberson , Da-Yuan Shih , Kamalesh K Srivastava , Michael J. Sullivan
发明人： Luc Belanger , Stephen L. Buchwalter , Leena Paivikki Buchwalter , Ajay P. Giri , Jonathan H. Griffith , Donald W. Henderson , Sung Kwon Kang , Eric H. Laine , Christian Lavoie , Paul A. Lauro , Valérie Anne Oberson , Da-Yuan Shih , Kamalesh K Srivastava , Michael J. Sullivan
IPC分类号： H01L21/44
CPC分类号： H01L24/12 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05599 , H01L2224/114 , H01L2224/11462 , H01L2224/1147 , H01L2224/116 , H01L2224/11849 , H01L2224/119 , H01L2224/13023 , H01L2224/13111 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/30107 , H01L2924/01083 , H01L2924/01049 , H01L2224/13099
摘要： An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.
摘要翻译：一种适于将微电子器件芯片倒装连接到封装的互连结构，包括二层，三层或四层限流冶金，包括粘附/反应阻挡层，并且具有与含锡的组分反应的焊料可湿性层无铅焊料，使得可焊接层在焊接期间可以完全消耗，但在焊接期间与无铅焊料接触后，阻挡层保持不变。一个或多个无铅焊料球选择性地位于焊料润湿层上，该无铅焊球包含锡作为主要成分和一种或多种合金成分。

5. 发明授权

US06438830B1 Process of producing plastic pin grid array 失效
标题翻译：生产塑料针格栅阵列的工艺
公开(公告)号：US06438830B1
公开(公告)日：2002-08-27
申请号：US09292163
申请日：1999-04-15
申请人： Eric P. Dibble , Eric H. Laine , Stephen W. MacQuarrie
发明人： Eric P. Dibble , Eric H. Laine , Stephen W. MacQuarrie
IPC分类号： H01R4320
CPC分类号： H05K3/308 , H01L23/49811 , H01L23/49827 , H01L2924/0002 , H01L2924/15312 , Y10T29/49139 , Y10T29/49147 , Y10T29/49151 , Y10T29/49165 , Y10T29/49181 , Y10T29/49208 , H01L2924/00
摘要： A pinning process including the steps of gold-plating through-holes in a laminate carrier and crimping old or gold-plated pin located in the through-holes to form a pin head on the top and a pin bulge on the bottom of the laminate carrier to produce a plastic pin grid array. A variety of mechanical forming processes may be employed to form the pin heads and pin bulges and cause the pin to at least partially, and preferably substantially, fill and contact the gold-plated through-hole including swage pinning, impact pinning, and double-die pinning operations. By combining the steps of gold-plating through-holes of a laminate carrier and using a mechanical pinning process to crimp a gold or gold-plated pin in the through-holes, a reliable mechanical and electrical connection may be established between the pin and the metal lines both inside and on the surface of the laminate carrier without the need for lead-containing solders and pastes.
摘要翻译：一种钉扎工艺，包括在叠层载体中镀金通孔的步骤，并且压接位于通孔中的旧镀金或镀金销，以在顶部形成销头，并在层压载体的底部上形成销凸起生产塑料针格栅阵列。可以采用各种机械成形工艺来形成销头和销凸起，并且使销至少部分地，优选地基本上填充和接触镀金通孔，包括模具钉扎，冲击钉扎和双重连接，死亡钉扎操作。通过结合层叠载体的镀金通孔的步骤，并使用机械钉扎工艺将金或镀金销压接在通孔中，可以在销和第二端之间建立可靠的机械和电连接金属线在层压载体的内部和表面上，而不需要含铅焊料和糊料。

6. 发明授权

US5952716A Pin attach structure for an electronic package 失效
标题翻译：电子封装的引脚连接结构
公开(公告)号：US5952716A
公开(公告)日：1999-09-14
申请号：US842859
申请日：1997-04-16
申请人： Eric P. Dibble , Eric H. Laine , Stephen W. MacQuarrie
发明人： Eric P. Dibble , Eric H. Laine , Stephen W. MacQuarrie
IPC分类号： H01L23/498 , H05K3/30 , H01L23/532
CPC分类号： H05K3/308 , H01L23/49811 , H01L23/49827 , H01L2924/0002 , H01L2924/15312 , Y10T29/49139 , Y10T29/49147 , Y10T29/49151 , Y10T29/49165 , Y10T29/49181 , Y10T29/49208
摘要： A pinning process including the steps of gold-plating through-holes in a laminate carrier and crimping a gold or gold-plated pin located in the through-holes to form a pin head on the top and a pin bulge on the bottom of the laminate carrier to produce a plastic pin grid array. A variety of mechanical forming processes may be employed to form the pin heads and pin bulges and cause the pin to at least partially, and preferably substantially, fill and contact the gold-plated through-hole including swage pinning, impact pinning, and double-die pinning operations. By combining the steps of gold-plating through-holes of a laminate carrier and using a mechanical pinning process to crimp a gold or gold-plated pin in the through-holes, a reliable mechanical and electrical connection may be established between the pin and the metal lines both inside and on the surface of the laminate carrier without the need for lead-containing solders and pastes.
摘要翻译：一种钉扎工艺，包括在层叠载体中镀金通孔的步骤，并且压接位于通孔中的金或镀金销，以在顶部形成销头，并在层压体的底部上形成销凸起载体产生塑料针格栅阵列。可以采用各种机械成形工艺来形成销头和销凸起，并且使销至少部分地，优选地基本上填充和接触镀金通孔，包括模具钉扎，冲击钉扎和双重连接，死亡钉扎操作。通过结合层叠载体的镀金通孔的步骤，并使用机械钉扎工艺将金或镀金销压接在通孔中，可以在销和第二端之间建立可靠的机械和电连接金属管线在层压载体的内部和表面上，而不需要含铅的焊料和糊料。

7. 发明授权

US5616958A Electronic package 失效
标题翻译：电子包装
公开(公告)号：US5616958A
公开(公告)日：1997-04-01
申请号：US378347
申请日：1995-01-25
申请人： Eric H. Laine , James W. Wilson
发明人： Eric H. Laine , James W. Wilson
IPC分类号： H01L21/56 , H01L23/14 , H01L23/29 , H01L23/31 , H01L23/498 , H01L23/538 , H01L33/62 , H01L23/34 , H01L23/48 , H01L23/495
CPC分类号： H01L24/32 , H01L21/563 , H01L23/142 , H01L23/293 , H01L23/3121 , H01L23/49816 , H01L23/49822 , H01L23/5385 , H01L2224/16225 , H01L2224/27013 , H01L2224/32225 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/83051 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/15787 , H01L2924/181 , H01L33/62
摘要： An electronic package which includes a thermally conductive, e.g., copper, member having a thin layer of dielectric material, e.g., polyimide, on at least one surface thereof. On the polyimide is provided the desired high density circuit pattern which is electrically connected, e.g., using solder or wirebonds, to the respective contact sites of a semiconductor chip. If wirebonds are used, the copper member preferably includes an indentation therein and the chip is secured, e.g., using adhesive, within this indentation. If solder is used to couple the chip, a plurality of small diameter solder elements are connected to respective contact sites of the chip and to respective ones of the pads and/or lines of the provided circuit pattern. Significantly, the pattern possesses lines and/or pads in one portion which are of high density and lines and/or pads in another portion which are of lesser density. The chip is coupled to the higher density portion of the circuitry which then may "fan out" to the lesser (and larger) density lines and/or pads of the other portion of the circuitry. The resulting package is also of a thin profile configuration and particularly adapted for being positioned on and electrically coupled to a PCB or the like substrate having conductors thereon.
摘要翻译：一种电子封装，其包括在其至少一个表面上具有例如聚酰亚胺的薄层的导热例如铜构件。在聚酰亚胺上提供了期望的高密度电路图案，其电连接到例如使用焊料或引线键合到半导体芯片的相应接触部位。如果使用了引线键，则铜构件优选地包括其中的凹陷，并且该芯片例如使用粘合剂固定在该凹口内。如果使用焊料来耦合芯片，则多个小直径焊料元件连接到芯片的相应接触位置以及所提供的电路图案的相应焊盘和/或线路中的相应的一个。重要的是，该图案具有一部分中具有较高密度的线和/或焊盘，另一部分具有较小密度的线和/或焊盘。芯片耦合到电路的较高密度部分，然后该电路可以“扇出”到电路的另一部分的较小（以及更大）的密度线和/或焊盘。所得到的封装也是薄型构造，并且特别适于被定位在具有导体的PCB或类似基板上并电耦合到其上。

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